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i965/fs: Implement FS_OPCODE_GET_BUFFER_SIZE

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Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
This commit is contained in:
Samuel Iglesias Gonsalvez 2015-04-13 16:55:49 +02:00
parent 65d7f5fe9f
commit b23eb643eb
5 changed files with 55 additions and 0 deletions
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1
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -1067,6 +1067,7 @@ enum opcode {
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
FS_OPCODE_GET_BUFFER_SIZE,
FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
FS_OPCODE_DISCARD_JUMP,
FS_OPCODE_SET_SAMPLE_ID,

1
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -883,6 +883,7 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
return 1;
case FS_OPCODE_FB_WRITE:
return 2;
case FS_OPCODE_GET_BUFFER_SIZE:
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
case SHADER_OPCODE_GEN4_SCRATCH_READ:
return 1;

3
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -431,6 +431,9 @@ private:
struct brw_reg *src);
void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
struct brw_reg sampler_index);
void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
struct brw_reg src,
struct brw_reg surf_index);
void generate_math_gen6(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,

47
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
View file

@ -543,6 +543,50 @@ fs_generator::generate_math_g45(fs_inst *inst,
BRW_MATH_PRECISION_FULL);
}
void
fs_generator::generate_get_buffer_size(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src,
struct brw_reg surf_index)
{
assert(devinfo->gen >= 7);
assert(surf_index.file == BRW_IMMEDIATE_VALUE);
uint32_t simd_mode;
int rlen = 4;
switch (inst->exec_size) {
case 8:
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
break;
case 16:
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
break;
default:
unreachable("Invalid width for texture instruction");
}
if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
rlen = 8;
dst = vec16(dst);
}
brw_SAMPLE(p,
retype(dst, BRW_REGISTER_TYPE_UW),
inst->base_mrf,
src,
surf_index.dw1.ud,
0,
GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
rlen, /* response length */
inst->mlen,
inst->header_size > 0,
simd_mode,
BRW_SAMPLER_RETURN_FORMAT_SINT32);
brw_mark_surface_used(prog_data, surf_index.dw1.ud);
}
void
fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
struct brw_reg sampler_index)
@ -1916,6 +1960,9 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
src[0].subnr = 4 * type_sz(src[0].type);
brw_MOV(p, dst, stride(src[0], 8, 4, 1));
break;
case FS_OPCODE_GET_BUFFER_SIZE:
generate_get_buffer_size(inst, dst, src[0], src[1]);
break;
case SHADER_OPCODE_TEX:
case FS_OPCODE_TXB:
case SHADER_OPCODE_TXD:

3
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -697,6 +697,9 @@ brw_instruction_name(enum opcode op)
case FS_OPCODE_PIXEL_Y:
return "pixel_y";
case FS_OPCODE_GET_BUFFER_SIZE:
return "fs_get_buffer_size";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7: