diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h
index 5171acc9b76..844a28d511c 100644
--- a/src/freedreno/common/freedreno_dev_info.h
+++ b/src/freedreno/common/freedreno_dev_info.h
@@ -125,6 +125,7 @@ struct fd_dev_info {
          struct {
             uint32_t RB_UNKNOWN_8E04_blit;
             uint32_t PC_POWER_CNTL;
+            uint32_t TPL1_DBG_ECO_CNTL;
          } magic;
       } a6xx;
    };
diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index b76c874883e..e13b5c6c2c1 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -126,6 +126,9 @@ class A6xxGPUInfo(GPUInfo):
         self.a6xx = Struct()
         self.a6xx.magic = Struct()
 
+        for name, val in template["magic"].items():
+            setattr(self.a6xx.magic, name, val)
+
         # Various "magic" register values:
         self.a6xx.magic.RB_UNKNOWN_8E04_blit = RB_UNKNOWN_8E04_blit
         self.a6xx.magic.PC_POWER_CNTL = PC_POWER_CNTL
@@ -136,6 +139,8 @@ class A6xxGPUInfo(GPUInfo):
         self.a6xx.has_8bpp_ubwc = True
 
         for name, val in template.items():
+            if name == "magic": # handled above
+                continue
             setattr(self.a6xx, name, val)
 
 # a2xx is really two sub-generations, a20x and a22x, but we don't currently
@@ -204,6 +209,9 @@ a6xx_gen1 = dict(
         ccu_cntl_gmem_unk2 = True,
         indirect_draw_wfm_quirk = True,
         depth_bounds_require_depth_test_quirk = True,
+        magic = dict(
+            TPL1_DBG_ECO_CNTL = 0x100000,
+        )
     )
 
 # a640, a680:
@@ -214,6 +222,9 @@ a6xx_gen2 = dict(
         has_z24uint_s8uint = True,
         indirect_draw_wfm_quirk = True,
         depth_bounds_require_depth_test_quirk = True, # TODO: check if true
+        magic = dict(
+            TPL1_DBG_ECO_CNTL = 0,
+        ),
     )
 
 # a650:
@@ -228,6 +239,10 @@ a6xx_gen3 = dict(
         has_sample_locations = True,
         has_ccu_flush_bug = True,
         has_8bpp_ubwc = False,
+        magic = dict(
+            # this seems to be a chicken bit that fixes cubic filtering:
+            TPL1_DBG_ECO_CNTL = 0x1000000,
+        ),
     )
 
 # a635, a660:
@@ -244,6 +259,9 @@ a6xx_gen4 = dict(
         has_8bpp_ubwc = False,
         has_lpac = True,
         has_shading_rate = True,
+        magic = dict(
+            TPL1_DBG_ECO_CNTL = 0x5008000,
+        ),
     )
 
 add_gpus([
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index bbf916a713c..aa12587025f 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -783,7 +783,8 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AE00, 0);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
    tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
-   tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL, 0x100000);
+   tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL,
+                        phys_dev->info->a6xx.magic.TPL1_DBG_ECO_CNTL);
    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
    tu_cs_emit_write_reg(cs, REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
 
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
index 47a31e51571..7fa28c99586 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c
@@ -1224,7 +1224,7 @@ fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 void
 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
 {
-   // struct fd_context *ctx = batch->ctx;
+   struct fd_screen *screen = batch->ctx->screen;
 
    if (!batch->nondraw) {
       trace_start_state_restore(&batch->trace, ring);
@@ -1248,7 +1248,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
    WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
    WRITE(REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
    WRITE(REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
-   WRITE(REG_A6XX_TPL1_DBG_ECO_CNTL, 0x100000);
+   WRITE(REG_A6XX_TPL1_DBG_ECO_CNTL, screen->info->a6xx.magic.TPL1_DBG_ECO_CNTL);
    WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
    WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);