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i965/fs: Factor out the register allocator setup to a separate function.
Besides separating out a logical step of the giant register allocator function, this now communicates a bunch of the allocator information through entries in brw_context, which will make this code partially reusable for caching the expensive allocator setup.
This commit is contained in:
Eric Anholt
parent
4e10d5825b
commit
b1f0bffd39
2 changed files with 105 additions and 66 deletions
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@ -748,6 +748,29 @@ struct brw_context
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* Pre-gen6, push constants live in the CURBE.
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*/
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uint32_t push_const_offset;
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/** @{ register allocator */
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struct ra_regs *regs;
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/** Array of the ra classes for the unaligned contiguous
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* register block sizes used.
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*/
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int *classes;
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/**
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* Mapping for register-allocated objects in *regs to the first
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* GRF for that object.
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*/
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uint8_t *ra_reg_to_grf;
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/**
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* ra class for the aligned pairs we use for PLN, which doesn't
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* appear in *classes.
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*/
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int aligned_pairs_class;
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/** @} */
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} wm;
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@ -87,6 +87,80 @@ fs_visitor::assign_regs_trivial()
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}
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static void
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brw_alloc_reg_set_for_classes(struct brw_context *brw,
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int *class_sizes,
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int class_count,
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int reg_width,
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int base_reg_count)
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{
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struct intel_context *intel = &brw->intel;
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/* Compute the total number of registers across all classes. */
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int ra_reg_count = 0;
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for (int i = 0; i < class_count; i++) {
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ra_reg_count += base_reg_count - (class_sizes[i] - 1);
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}
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ralloc_free(brw->wm.ra_reg_to_grf);
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brw->wm.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
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ralloc_free(brw->wm.regs);
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brw->wm.regs = ra_alloc_reg_set(ra_reg_count);
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ralloc_free(brw->wm.classes);
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brw->wm.classes = ralloc_array(brw, int, class_count + 1);
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brw->wm.aligned_pairs_class = -1;
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/* Now, add the registers to their classes, and add the conflicts
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* between them and the base GRF registers (and also each other).
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*/
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int reg = 0;
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int pairs_base_reg = 0;
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int pairs_reg_count = 0;
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for (int i = 0; i < class_count; i++) {
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int class_reg_count = base_reg_count - (class_sizes[i] - 1);
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brw->wm.classes[i] = ra_alloc_reg_class(brw->wm.regs);
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/* Save this off for the aligned pair class at the end. */
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if (class_sizes[i] == 2) {
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pairs_base_reg = reg;
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pairs_reg_count = class_reg_count;
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}
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for (int j = 0; j < class_reg_count; j++) {
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ra_class_add_reg(brw->wm.regs, brw->wm.classes[i], reg);
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brw->wm.ra_reg_to_grf[reg] = j;
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for (int base_reg = j;
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base_reg < j + class_sizes[i];
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base_reg++) {
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ra_add_transitive_reg_conflict(brw->wm.regs, base_reg, reg);
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}
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reg++;
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}
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}
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assert(reg == ra_reg_count);
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/* Add a special class for aligned pairs, which we'll put delta_x/y
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* in on gen5 so that we can do PLN.
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*/
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if (brw->has_pln && reg_width == 1 && intel->gen < 6) {
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brw->wm.aligned_pairs_class = ra_alloc_reg_class(brw->wm.regs);
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for (int i = 0; i < pairs_reg_count; i++) {
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if ((brw->wm.ra_reg_to_grf[pairs_base_reg + i] & 1) == 0) {
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ra_class_add_reg(brw->wm.regs, brw->wm.aligned_pairs_class,
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pairs_base_reg + i);
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}
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}
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class_count++;
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}
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ra_set_finalize(brw->wm.regs);
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}
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bool
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fs_visitor::assign_regs()
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{
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@ -102,7 +176,6 @@ fs_visitor::assign_regs()
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int base_reg_count = (BRW_MAX_GRF - first_assigned_grf) / reg_width;
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int class_sizes[base_reg_count];
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int class_count = 0;
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int aligned_pairs_class = -1;
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calculate_live_intervals();
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@ -137,76 +210,20 @@ fs_visitor::assign_regs()
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}
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}
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/* Compute the total number of registers across all classes. */
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int ra_reg_count = 0;
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for (int i = 0; i < class_count; i++) {
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ra_reg_count += base_reg_count - (class_sizes[i] - 1);
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}
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brw_alloc_reg_set_for_classes(brw, class_sizes, class_count,
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reg_width, base_reg_count);
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struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
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uint8_t ra_reg_to_grf[ra_reg_count];
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int classes[class_count + 1];
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/* Now, add the registers to their classes, and add the conflicts
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* between them and the base GRF registers (and also each other).
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*/
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int reg = 0;
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int pairs_base_reg = 0;
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int pairs_reg_count = 0;
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for (int i = 0; i < class_count; i++) {
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int class_reg_count = base_reg_count - (class_sizes[i] - 1);
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classes[i] = ra_alloc_reg_class(regs);
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/* Save this off for the aligned pair class at the end. */
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if (class_sizes[i] == 2) {
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pairs_base_reg = reg;
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pairs_reg_count = class_reg_count;
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}
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for (int j = 0; j < class_reg_count; j++) {
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ra_class_add_reg(regs, classes[i], reg);
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ra_reg_to_grf[reg] = j;
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for (int base_reg = j;
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base_reg < j + class_sizes[i];
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base_reg++) {
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ra_add_transitive_reg_conflict(regs, base_reg, reg);
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}
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reg++;
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}
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}
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assert(reg == ra_reg_count);
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/* Add a special class for aligned pairs, which we'll put delta_x/y
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* in on gen5 so that we can do PLN.
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*/
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if (brw->has_pln && reg_width == 1 && intel->gen < 6) {
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aligned_pairs_class = ra_alloc_reg_class(regs);
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for (int i = 0; i < pairs_reg_count; i++) {
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if ((ra_reg_to_grf[pairs_base_reg + i] & 1) == 0) {
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ra_class_add_reg(regs, aligned_pairs_class,
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pairs_base_reg + i);
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}
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}
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class_count++;
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}
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ra_set_finalize(regs);
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struct ra_graph *g = ra_alloc_interference_graph(regs,
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struct ra_graph *g = ra_alloc_interference_graph(brw->wm.regs,
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this->virtual_grf_next);
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for (int i = 0; i < this->virtual_grf_next; i++) {
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for (int c = 0; c < class_count; c++) {
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if (class_sizes[c] == this->virtual_grf_sizes[i]) {
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if (aligned_pairs_class >= 0 &&
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if (brw->wm.aligned_pairs_class >= 0 &&
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this->delta_x.reg == i) {
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ra_set_node_class(g, i, aligned_pairs_class);
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ra_set_node_class(g, i, brw->wm.aligned_pairs_class);
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} else {
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ra_set_node_class(g, i, classes[c]);
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ra_set_node_class(g, i, brw->wm.classes[c]);
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}
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break;
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}
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@ -237,7 +254,6 @@ fs_visitor::assign_regs()
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ralloc_free(g);
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ralloc_free(regs);
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return false;
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}
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@ -250,7 +266,8 @@ fs_visitor::assign_regs()
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for (int i = 0; i < this->virtual_grf_next; i++) {
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int reg = ra_get_node_reg(g, i);
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hw_reg_mapping[i] = first_assigned_grf + ra_reg_to_grf[reg] * reg_width;
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hw_reg_mapping[i] = (first_assigned_grf +
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brw->wm.ra_reg_to_grf[reg] * reg_width);
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this->grf_used = MAX2(this->grf_used,
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hw_reg_mapping[i] + this->virtual_grf_sizes[i] *
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reg_width);
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@ -265,7 +282,6 @@ fs_visitor::assign_regs()
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}
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ralloc_free(g);
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ralloc_free(regs);
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return true;
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}
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