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radeon: remove unused radeon_compat.c
This commit is contained in:
Dave Airlie
parent
f8c2beccd4
commit
b1b7bc66a4
1 changed files with 0 additions and 301 deletions
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@ -1,301 +0,0 @@
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/**************************************************************************
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Copyright 2002 ATI Technologies Inc., Ontario, Canada, and
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Tungsten Graphics Inc., Austin, Texas.
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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on the rights to use, copy, modify, merge, publish, distribute, sub
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license, and/or sell copies of the Software, and to permit persons to whom
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the Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice (including the next
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paragraph) shall be included in all copies or substantial portions of the
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Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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ATI, TUNGSTEN GRAPHICS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Keith Whitwell <keith@tungstengraphics.com>
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*
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*/
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#include "main/glheader.h"
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#include "main/imports.h"
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#include "radeon_context.h"
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#include "radeon_state.h"
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#include "radeon_ioctl.h"
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static struct {
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int start;
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int len;
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const char *name;
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} packet[RADEON_MAX_STATE_PACKETS] = {
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{ RADEON_PP_MISC,7,"RADEON_PP_MISC" },
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{ RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
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{ RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
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{ RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
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{ RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
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{ RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
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{ RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
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{ RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
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{ RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
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{ RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
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{ RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
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{ RADEON_RE_MISC,1,"RADEON_RE_MISC" },
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{ RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
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{ RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
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{ RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
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{ RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
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{ RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
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{ RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
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{ RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
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{ RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
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{ RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
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};
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static void radeonCompatEmitPacket( radeonContextPtr rmesa,
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struct radeon_state_atom *state )
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{
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drm_radeon_sarea_t *sarea = rmesa->sarea;
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drm_radeon_context_regs_t *ctx = &sarea->context_state;
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drm_radeon_texture_regs_t *tex0 = &sarea->tex_state[0];
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drm_radeon_texture_regs_t *tex1 = &sarea->tex_state[1];
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int i;
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int *buf = state->cmd;
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for ( i = 0 ; i < state->cmd_size ; ) {
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drm_radeon_cmd_header_t *header = (drm_radeon_cmd_header_t *)&buf[i++];
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if (RADEON_DEBUG & DEBUG_STATE)
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fprintf(stderr, "%s %d: %s\n", __FUNCTION__, header->packet.packet_id,
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packet[(int)header->packet.packet_id].name);
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switch (header->packet.packet_id) {
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case RADEON_EMIT_PP_MISC:
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ctx->pp_misc = buf[i++];
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ctx->pp_fog_color = buf[i++];
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ctx->re_solid_color = buf[i++];
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ctx->rb3d_blendcntl = buf[i++];
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ctx->rb3d_depthoffset = buf[i++];
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ctx->rb3d_depthpitch = buf[i++];
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ctx->rb3d_zstencilcntl = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_CONTEXT;
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break;
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case RADEON_EMIT_PP_CNTL:
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ctx->pp_cntl = buf[i++];
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ctx->rb3d_cntl = buf[i++];
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ctx->rb3d_coloroffset = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_CONTEXT;
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break;
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case RADEON_EMIT_RB3D_COLORPITCH:
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ctx->rb3d_colorpitch = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_CONTEXT;
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break;
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case RADEON_EMIT_RE_LINE_PATTERN:
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ctx->re_line_pattern = buf[i++];
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ctx->re_line_state = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_LINE;
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break;
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case RADEON_EMIT_SE_LINE_WIDTH:
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ctx->se_line_width = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_LINE;
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break;
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case RADEON_EMIT_PP_LUM_MATRIX:
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ctx->pp_lum_matrix = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_BUMPMAP;
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break;
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case RADEON_EMIT_PP_ROT_MATRIX_0:
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ctx->pp_rot_matrix_0 = buf[i++];
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ctx->pp_rot_matrix_1 = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_BUMPMAP;
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break;
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case RADEON_EMIT_RB3D_STENCILREFMASK:
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ctx->rb3d_stencilrefmask = buf[i++];
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ctx->rb3d_ropcntl = buf[i++];
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ctx->rb3d_planemask = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_MASKS;
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break;
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case RADEON_EMIT_SE_VPORT_XSCALE:
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ctx->se_vport_xscale = buf[i++];
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ctx->se_vport_xoffset = buf[i++];
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ctx->se_vport_yscale = buf[i++];
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ctx->se_vport_yoffset = buf[i++];
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ctx->se_vport_zscale = buf[i++];
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ctx->se_vport_zoffset = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_VIEWPORT;
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break;
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case RADEON_EMIT_SE_CNTL:
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ctx->se_cntl = buf[i++];
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ctx->se_coord_fmt = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_CONTEXT | RADEON_UPLOAD_VERTFMT;
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break;
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case RADEON_EMIT_SE_CNTL_STATUS:
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ctx->se_cntl_status = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_SETUP;
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break;
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case RADEON_EMIT_RE_MISC:
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ctx->re_misc = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_MISC;
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break;
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case RADEON_EMIT_PP_TXFILTER_0:
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tex0->pp_txfilter = buf[i++];
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tex0->pp_txformat = buf[i++];
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tex0->pp_txoffset = buf[i++];
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tex0->pp_txcblend = buf[i++];
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tex0->pp_txablend = buf[i++];
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tex0->pp_tfactor = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_TEX0;
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break;
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case RADEON_EMIT_PP_BORDER_COLOR_0:
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tex0->pp_border_color = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_TEX0;
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break;
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case RADEON_EMIT_PP_TXFILTER_1:
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tex1->pp_txfilter = buf[i++];
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tex1->pp_txformat = buf[i++];
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tex1->pp_txoffset = buf[i++];
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tex1->pp_txcblend = buf[i++];
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tex1->pp_txablend = buf[i++];
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tex1->pp_tfactor = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_TEX1;
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break;
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case RADEON_EMIT_PP_BORDER_COLOR_1:
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tex1->pp_border_color = buf[i++];
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sarea->dirty |= RADEON_UPLOAD_TEX1;
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break;
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case RADEON_EMIT_SE_ZBIAS_FACTOR:
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i++;
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i++;
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break;
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case RADEON_EMIT_PP_TXFILTER_2:
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case RADEON_EMIT_PP_BORDER_COLOR_2:
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case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
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case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
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default:
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/* These states aren't understood by radeon drm 1.1 */
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fprintf(stderr, "Tried to emit unsupported state\n");
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return;
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}
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}
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}
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static void radeonCompatEmitStateLocked( radeonContextPtr rmesa )
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{
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struct radeon_state_atom *atom;
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if (RADEON_DEBUG & (DEBUG_STATE|DEBUG_PRIMS))
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fprintf(stderr, "%s\n", __FUNCTION__);
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if (!rmesa->hw.is_dirty && !rmesa->hw.all_dirty)
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return;
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foreach(atom, &rmesa->hw.atomlist) {
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if (rmesa->hw.all_dirty)
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atom->dirty = GL_TRUE;
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if (atom->is_tcl)
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atom->dirty = GL_FALSE;
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if (atom->dirty)
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radeonCompatEmitPacket(rmesa, atom);
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}
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rmesa->hw.is_dirty = GL_FALSE;
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rmesa->hw.all_dirty = GL_FALSE;
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}
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static void radeonCompatEmitPrimitiveLocked( radeonContextPtr rmesa,
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GLuint hw_primitive,
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GLuint nverts,
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drm_clip_rect_t *pbox,
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GLuint nbox )
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{
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int i;
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for ( i = 0 ; i < nbox ; ) {
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int nr = MIN2( i + RADEON_NR_SAREA_CLIPRECTS, nbox );
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drm_clip_rect_t *b = rmesa->sarea->boxes;
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drm_radeon_vertex_t vtx;
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rmesa->sarea->dirty |= RADEON_UPLOAD_CLIPRECTS;
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rmesa->sarea->nbox = nr - i;
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for ( ; i < nr ; i++)
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*b++ = pbox[i];
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if (RADEON_DEBUG & DEBUG_IOCTL)
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fprintf(stderr,
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"RadeonFlushVertexBuffer: prim %x buf %d verts %d "
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"disc %d nbox %d\n",
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hw_primitive,
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rmesa->dma.current.buf->buf->idx,
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nverts,
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nr == nbox,
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rmesa->sarea->nbox );
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vtx.prim = hw_primitive;
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vtx.idx = rmesa->dma.current.buf->buf->idx;
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vtx.count = nverts;
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vtx.discard = (nr == nbox);
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drmCommandWrite( rmesa->dri.fd,
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DRM_RADEON_VERTEX,
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&vtx, sizeof(vtx));
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}
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}
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/* No 'start' for 1.1 vertices ioctl: only one vertex prim/buffer!
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*/
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void radeonCompatEmitPrimitive( radeonContextPtr rmesa,
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GLuint vertex_format,
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GLuint hw_primitive,
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GLuint nrverts )
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{
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if (RADEON_DEBUG & DEBUG_IOCTL)
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fprintf(stderr, "%s\n", __FUNCTION__);
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LOCK_HARDWARE( rmesa );
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radeonCompatEmitStateLocked( rmesa );
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rmesa->sarea->vc_format = vertex_format;
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if (rmesa->state.scissor.enabled) {
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radeonCompatEmitPrimitiveLocked( rmesa,
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hw_primitive,
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nrverts,
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rmesa->state.scissor.pClipRects,
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rmesa->state.scissor.numClipRects );
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}
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else {
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radeonCompatEmitPrimitiveLocked( rmesa,
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hw_primitive,
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nrverts,
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rmesa->pClipRects,
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rmesa->numClipRects );
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}
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UNLOCK_HARDWARE( rmesa );
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}
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