From b1af36163ced92e283435fbd7f227f2706cedec7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 10 Jul 2022 23:12:06 -0400 Subject: [PATCH] radeonsi/gfx11: use correct VGT_TESS_DISTRIBUTION settings Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_state.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 2d826486137..a87e6a48cc6 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5706,7 +5706,14 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) if (sctx->gfx_level >= GFX8) { unsigned vgt_tess_distribution; - if (sctx->gfx_level >= GFX9) { + if (sctx->gfx_level >= GFX11) { + /* ACCUM fields changed their meaning. */ + vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(255) | + S_028B50_ACCUM_TRI(255) | + S_028B50_ACCUM_QUAD(255) | + S_028B50_DONUT_SPLIT_GFX9(24) | + S_028B50_TRAP_SPLIT(6); + } else if (sctx->gfx_level >= GFX9) { vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(12) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) |