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intel: simplify is_haswell checks, part 2

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Few cases that were not handled by sed.

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10810>
This commit is contained in:
Marcin Ślusarz 2021-05-14 18:12:28 +02:00 • committed by Marge Bot
parent 3340d5ee02
commit b1933d769f
5 changed files with 10 additions and 14 deletions
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12
src/intel/vulkan/anv_device.c
View file

@ -258,8 +258,7 @@ get_device_extensions(const struct anv_physical_device *device,
.EXT_buffer_device_address = device->has_a64_buffer_access,
.EXT_calibrated_timestamps = device->has_reg_timestamp,
.EXT_color_write_enable = true,
.EXT_conditional_rendering = device->info.ver >= 8 ||
device->info.is_haswell,
.EXT_conditional_rendering = device->info.verx10 >= 75,
.EXT_conservative_rasterization = device->info.ver >= 9,
.EXT_custom_border_color = device->info.ver >= 8,
.EXT_depth_clip_enable = true,
@ -1397,10 +1396,8 @@ void anv_GetPhysicalDeviceFeatures2(
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
(VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
features->conditionalRendering = pdevice->info.ver >= 8 ||
pdevice->info.is_haswell;
features->inheritedConditionalRendering = pdevice->info.ver >= 8 ||
pdevice->info.is_haswell;
features->conditionalRendering = pdevice->info.verx10 >= 75;
features->inheritedConditionalRendering = pdevice->info.verx10 >= 75;
break;
}
@ -2533,8 +2530,7 @@ void anv_GetPhysicalDeviceProperties2(
props->transformFeedbackStreamsLinesTriangles = false;
props->transformFeedbackRasterizationStreamSelect = false;
/* This requires MI_MATH */
props->transformFeedbackDraw = pdevice->info.is_haswell ||
pdevice->info.ver >= 8;
props->transformFeedbackDraw = pdevice->info.verx10 >= 75;
break;
}

4
src/intel/vulkan/anv_nir_apply_pipeline_layout.c
View file

@ -1187,7 +1187,7 @@ static void
lower_gfx7_tex_swizzle(nir_builder *b, nir_tex_instr *tex, unsigned plane,
struct apply_pipeline_layout_state *state)
{
assert(state->pdevice->info.ver == 7 && !state->pdevice->info.is_haswell);
assert(state->pdevice->info.verx10 == 70);
if (tex->sampler_dim == GLSL_SAMPLER_DIM_BUF ||
nir_tex_instr_is_query(tex) ||
tex->op == nir_texop_tg4 || /* We can't swizzle TG4 */
@ -1259,7 +1259,7 @@ lower_tex(nir_builder *b, nir_tex_instr *tex,
/* On Ivy Bridge and Bay Trail, we have to swizzle in the shader. Do this
* before we lower the derefs away so we can still find the descriptor.
*/
if (state->pdevice->info.ver == 7 && !state->pdevice->info.is_haswell)
if (state->pdevice->info.verx10 == 70)
lower_gfx7_tex_swizzle(b, tex, plane, state);
b->cursor = nir_before_instr(&tex->instr);

2
src/intel/vulkan/anv_nir_compute_push_layout.c
View file

@ -75,7 +75,7 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
const bool has_push_intrinsic = push_start <= push_end;
const bool push_ubo_ranges =
(pdevice->info.ver >= 8 || pdevice->info.is_haswell) &&
pdevice->info.verx10 >= 75 &&
has_const_ubo && nir->info.stage != MESA_SHADER_COMPUTE;
if (push_ubo_ranges && robust_buffer_access) {

4
src/mesa/drivers/dri/i965/brw_batch.c
View file

@ -1257,7 +1257,7 @@ brw_load_register_imm64(struct brw_context *brw, uint32_t reg, uint64_t imm)
void
brw_load_register_reg(struct brw_context *brw, uint32_t dest, uint32_t src)
{
assert(brw->screen->devinfo.ver >= 8 || brw->screen->devinfo.is_haswell);
assert(brw->screen->devinfo.verx10 >= 75);
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
@ -1272,7 +1272,7 @@ brw_load_register_reg(struct brw_context *brw, uint32_t dest, uint32_t src)
void
brw_load_register_reg64(struct brw_context *brw, uint32_t dest, uint32_t src)
{
assert(brw->screen->devinfo.ver >= 8 || brw->screen->devinfo.is_haswell);
assert(brw->screen->devinfo.verx10 >= 75);
BEGIN_BATCH(6);
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));

2
src/mesa/drivers/dri/i965/brw_draw_upload.c
View file

@ -254,7 +254,7 @@ brw_get_vertex_surface_type(struct brw_context *brw,
int size = glformat->Size;
const struct intel_device_info *devinfo = &brw->screen->devinfo;
const bool is_ivybridge_or_older =
devinfo->ver <= 7 && !devinfo->is_baytrail && !devinfo->is_haswell;
devinfo->verx10 <= 70 && !devinfo->is_baytrail;
if (INTEL_DEBUG & DEBUG_VERTS)
fprintf(stderr, "type %s size %d normalized %d\n",