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i965: Don't forget to subtract mt->first_level in minify calls.

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This fixes fbo-clear-formats GL_ARB_depth_texture on Ironlake, which
regressed since commit f128bcc7c2
("i965: Drop mt->levels[].width/height.")  intel_miptree_copy_slice was
calling minify(.., 7) on a 2x2 texture with mt->first_level == 7.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75292
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke 2014-02-22 23:47:30 -08:00
parent ac0a8b9540
commit b18871c863
5 changed files with 13 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/mesa/drivers/dri/i965/brw_blorp.cpp
View file

@ -68,8 +68,8 @@ brw_blorp_mip_info::set(struct intel_mipmap_tree *mt,
this->mt = mt;
this->level = level;
this->layer = layer;
this->width = minify(mt->physical_width0, level);
this->height = minify(mt->physical_height0, level);
this->width = minify(mt->physical_width0, level - mt->first_level);
this->height = minify(mt->physical_height0, level - mt->first_level);
intel_miptree_get_image_offset(mt, level, layer, &x_offset, &y_offset);
}

5
src/mesa/drivers/dri/i965/brw_clear.c
View file

@ -155,8 +155,9 @@ brw_fast_clear_depth(struct gl_context *ctx)
* width of the map (LOD0) is not multiple of 16, fast clear
* optimization must be disabled.
*/
if (brw->gen == 6 && (minify(mt->physical_width0,
depth_irb->mt_level) % 16) != 0)
if (brw->gen == 6 &&
(minify(mt->physical_width0,
depth_irb->mt_level - mt->first_level) % 16) != 0)
return false;
/* FALLTHROUGH */

4
src/mesa/drivers/dri/i965/intel_blit.c
View file

@ -219,10 +219,10 @@ intel_miptree_blit(struct brw_context *brw,
intel_miptree_resolve_color(brw, dst_mt);
if (src_flip)
src_y = minify(src_mt->physical_height0, src_level) - src_y - height;
src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
if (dst_flip)
dst_y = minify(dst_mt->physical_height0, dst_level) - dst_y - height;
dst_y = minify(dst_mt->physical_height0, dst_level - dst_mt->first_level) - dst_y - height;
int src_pitch = src_mt->region->pitch;
if (src_flip != dst_flip)

8
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -876,8 +876,8 @@ intel_miptree_match_image(struct intel_mipmap_tree *mt,
* minification. This will also catch images not present in the
* tree, changed targets, etc.
*/
if (width != minify(mt->logical_width0, level) ||
height != minify(mt->logical_height0, level) ||
if (width != minify(mt->logical_width0, level - mt->first_level) ||
height != minify(mt->logical_height0, level - mt->first_level) ||
depth != level_depth) {
return false;
}
@ -1041,8 +1041,8 @@ intel_miptree_copy_slice(struct brw_context *brw,
{
mesa_format format = src_mt->format;
uint32_t width = minify(src_mt->physical_width0, level);
uint32_t height = minify(src_mt->physical_height0, level);
uint32_t width = minify(src_mt->physical_width0, level - src_mt->first_level);
uint32_t height = minify(src_mt->physical_height0, level - src_mt->first_level);
int slice;
if (face > 0)

4
src/mesa/drivers/dri/i965/intel_screen.c
View file

@ -329,8 +329,8 @@ intel_setup_image_from_mipmap_tree(struct brw_context *brw, __DRIimage *image,
intel_region_get_tile_masks(mt->region, &mask_x, &mask_y, false);
intel_miptree_get_image_offset(mt, level, zoffset, &draw_x, &draw_y);
image->width = minify(mt->physical_width0, level);
image->height = minify(mt->physical_height0, level);
image->width = minify(mt->physical_width0, level - mt->first_level);
image->height = minify(mt->physical_height0, level - mt->first_level);
image->tile_x = draw_x & mask_x;
image->tile_y = draw_y & mask_y;