diff --git a/src/amd/vulkan/00-radv-defaults.conf b/src/amd/vulkan/00-radv-defaults.conf
index 2587e950711..9800bffe89a 100644
--- a/src/amd/vulkan/00-radv-defaults.conf
+++ b/src/amd/vulkan/00-radv-defaults.conf
@@ -126,10 +126,6 @@ Application bugs worked around in this file:
-
-
-
-
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 3db01f6e4b3..eb41051a329 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -973,7 +973,6 @@ static const driOptionDescription radv_dri_options[] = {
DRI_CONF_RADV_DISABLE_DCC(false)
DRI_CONF_RADV_REPORT_APU_AS_DGPU(false)
DRI_CONF_RADV_REQUIRE_ETC2(false)
- DRI_CONF_RADV_DISABLE_HTILE_LAYERS(false)
DRI_CONF_RADV_DISABLE_ANISO_SINGLE_LEVEL(false)
DRI_CONF_RADV_DISABLE_SINKING_LOAD_INPUT_FS(false)
DRI_CONF_SECTION_END
@@ -1022,9 +1021,6 @@ radv_init_dri_options(struct radv_instance *instance)
instance->report_apu_as_dgpu =
driQueryOptionb(&instance->dri_options, "radv_report_apu_as_dgpu");
- instance->disable_htile_layers =
- driQueryOptionb(&instance->dri_options, "radv_disable_htile_layers");
-
instance->disable_aniso_single_level =
driQueryOptionb(&instance->dri_options, "radv_disable_aniso_single_level");
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 84b2d9ef61f..2d303bd4e1b 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -362,9 +362,6 @@ radv_use_htile_for_image(const struct radv_device *device, const struct radv_ima
!device->attachment_vrs_enabled)
return false;
- if (device->instance->disable_htile_layers && image->info.array_size > 1)
- return false;
-
return (image->info.levels == 1 || use_htile_for_mips) && !image->shareable;
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 88466f1a8ee..fe97a61b21a 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -357,7 +357,6 @@ struct radv_instance {
bool disable_shrink_image_store;
bool absolute_depth_bias;
bool report_apu_as_dgpu;
- bool disable_htile_layers;
bool disable_aniso_single_level;
bool zero_vram;
bool disable_sinking_load_input_fs;
diff --git a/src/util/driconf.h b/src/util/driconf.h
index a80ad910a5f..ad4826abf8d 100644
--- a/src/util/driconf.h
+++ b/src/util/driconf.h
@@ -574,10 +574,6 @@
DRI_CONF_OPT_B(radv_require_etc2, def, \
"Implement emulated ETC2 on HW that does not support it")
-#define DRI_CONF_RADV_DISABLE_HTILE_LAYERS(def) \
- DRI_CONF_OPT_B(radv_disable_htile_layers, def, \
- "Disable HTILE for layered depth/stencil formats")
-
#define DRI_CONF_RADV_DISABLE_ANISO_SINGLE_LEVEL(def) \
DRI_CONF_OPT_B(radv_disable_aniso_single_level, def, \
"Disable anisotropic filtering for single level images")