From b0829c6af70a4f566a7a6a205b26b1cffe55e29c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 8 Oct 2020 16:52:36 +0200 Subject: [PATCH] radv: replace RADV_ALPHA_ADJUST by AC_FETCH_FORMAT Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/common/ac_shader_util.h | 1 + src/amd/compiler/aco_instruction_selection.cpp | 14 +++++++------- src/amd/vulkan/radv_nir_to_llvm.c | 12 ++++++------ src/amd/vulkan/radv_pipeline.c | 12 ++++++------ src/amd/vulkan/radv_private.h | 2 +- src/amd/vulkan/radv_shader.h | 11 +++-------- 6 files changed, 24 insertions(+), 28 deletions(-) diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h index 738cc32252c..8afee13b077 100644 --- a/src/amd/common/ac_shader_util.h +++ b/src/amd/common/ac_shader_util.h @@ -75,6 +75,7 @@ enum ac_fetch_format AC_FETCH_FORMAT_SSCALED, AC_FETCH_FORMAT_UINT, AC_FETCH_FORMAT_SINT, + AC_FETCH_FORMAT_NONE, }; unsigned ac_get_spi_shader_z_format(bool writes_z, bool writes_stencil, bool writes_samplemask); diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 27da22fd2e8..46d07fd1eca 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -4509,7 +4509,7 @@ Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alph { Builder bld(ctx->program, ctx->block); - if (adjustment == RADV_ALPHA_ADJUST_SSCALED) + if (adjustment == AC_FETCH_FORMAT_SSCALED) alpha = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), alpha); /* For the integer-like cases, do a natural sign extension. @@ -4518,15 +4518,15 @@ Temp adjust_vertex_fetch_alpha(isel_context *ctx, unsigned adjustment, Temp alph * and happen to contain 0, 1, 2, 3 as the two LSBs of the * exponent. */ - alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == RADV_ALPHA_ADJUST_SNORM ? 7u : 30u), alpha); + alpha = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), Operand(adjustment == AC_FETCH_FORMAT_SNORM ? 7u : 30u), alpha); alpha = bld.vop2(aco_opcode::v_ashrrev_i32, bld.def(v1), Operand(30u), alpha); /* Convert back to the right type. */ - if (adjustment == RADV_ALPHA_ADJUST_SNORM) { + if (adjustment == AC_FETCH_FORMAT_SNORM) { alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha); Temp clamp = bld.vopc(aco_opcode::v_cmp_le_f32, bld.hint_vcc(bld.def(bld.lm)), Operand(0xbf800000u), alpha); alpha = bld.vop2(aco_opcode::v_cndmask_b32, bld.def(v1), Operand(0xbf800000u), alpha, clamp); - } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) { + } else if (adjustment == AC_FETCH_FORMAT_SSCALED) { alpha = bld.vop1(aco_opcode::v_cvt_f32_i32, bld.def(v1), alpha); } @@ -4553,6 +4553,7 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr) uint32_t attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[location]; uint32_t attrib_stride = ctx->options->key.vs.vertex_attribute_strides[location]; unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[location]; + enum ac_fetch_format alpha_adjust = ctx->options->key.vs.alpha_adjust[location]; unsigned dfmt = attrib_format & 0xf; unsigned nfmt = (attrib_format >> 4) & 0x7; @@ -4560,7 +4561,6 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr) unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component; unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels); - unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (location * 2)) & 3; bool post_shuffle = ctx->options->key.vs.post_shuffle & (1 << location); if (post_shuffle) num_channels = MAX2(num_channels, 3); @@ -4680,7 +4680,7 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr) Temp fetch_dst; if (channel_start == 0 && fetch_bytes == dst.bytes() && !post_shuffle && - !expanded && (alpha_adjust == RADV_ALPHA_ADJUST_NONE || + !expanded && (alpha_adjust == AC_FETCH_FORMAT_NONE || num_channels <= 3)) { direct_fetch = true; fetch_dst = dst; @@ -4726,7 +4726,7 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr) unsigned idx = i + component; if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) { Temp channel = channels[swizzle[idx]]; - if (idx == 3 && alpha_adjust != RADV_ALPHA_ADJUST_NONE) + if (idx == 3 && alpha_adjust != AC_FETCH_FORMAT_NONE) channel = adjust_vertex_fetch_alpha(ctx, alpha_adjust, channel); vec->operands[i] = Operand(channel); diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 00bada4f506..952e73f6d9f 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -1045,14 +1045,14 @@ adjust_vertex_fetch_alpha(struct radv_shader_context *ctx, unsigned adjustment, LLVMValueRef alpha) { - if (adjustment == RADV_ALPHA_ADJUST_NONE) + if (adjustment == AC_FETCH_FORMAT_NONE) return alpha; LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0); alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, ""); - if (adjustment == RADV_ALPHA_ADJUST_SSCALED) + if (adjustment == AC_FETCH_FORMAT_SSCALED) alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, ""); else alpha = ac_to_integer(&ctx->ac, alpha); @@ -1064,18 +1064,18 @@ adjust_vertex_fetch_alpha(struct radv_shader_context *ctx, * exponent. */ alpha = LLVMBuildShl(ctx->ac.builder, alpha, - adjustment == RADV_ALPHA_ADJUST_SNORM ? + adjustment == AC_FETCH_FORMAT_SNORM ? LLVMConstInt(ctx->ac.i32, 7, 0) : c30, ""); alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, ""); /* Convert back to the right type. */ - if (adjustment == RADV_ALPHA_ADJUST_SNORM) { + if (adjustment == AC_FETCH_FORMAT_SNORM) { LLVMValueRef clamp; LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0); alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, ""); clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, ""); alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, ""); - } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) { + } else if (adjustment == AC_FETCH_FORMAT_SSCALED) { alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, ""); } @@ -1177,6 +1177,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx, unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index]; unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index]; unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index]; + unsigned alpha_adjust = ctx->args->options->key.vs.alpha_adjust[attrib_index]; if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) { /* Always load, at least, 3 channels for formats that @@ -1272,7 +1273,6 @@ handle_vs_input_decl(struct radv_shader_context *ctx, } } - unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3; output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]); for (unsigned chan = 0; chan < 4; chan++) { diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index eec74c876c5..9556104c687 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2449,21 +2449,21 @@ radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline, switch(format) { case VK_FORMAT_A2R10G10B10_SNORM_PACK32: case VK_FORMAT_A2B10G10R10_SNORM_PACK32: - adjust = RADV_ALPHA_ADJUST_SNORM; + adjust = AC_FETCH_FORMAT_SNORM; break; case VK_FORMAT_A2R10G10B10_SSCALED_PACK32: case VK_FORMAT_A2B10G10R10_SSCALED_PACK32: - adjust = RADV_ALPHA_ADJUST_SSCALED; + adjust = AC_FETCH_FORMAT_SSCALED; break; case VK_FORMAT_A2R10G10B10_SINT_PACK32: case VK_FORMAT_A2B10G10R10_SINT_PACK32: - adjust = RADV_ALPHA_ADJUST_SINT; + adjust = AC_FETCH_FORMAT_SINT; break; default: - adjust = 0; + adjust = AC_FETCH_FORMAT_NONE; break; } - key.vertex_alpha_adjust |= adjust << (2 * location); + key.vertex_alpha_adjust[location] = adjust; } switch (desc->format) { @@ -2531,7 +2531,6 @@ radv_fill_shader_keys(struct radv_device *device, nir_shader **nir) { keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs; - keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust; keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle; for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) { keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i]; @@ -2539,6 +2538,7 @@ radv_fill_shader_keys(struct radv_device *device, keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i]; keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i]; keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i]; + keys[MESA_SHADER_VERTEX].vs.alpha_adjust[i] = key->vertex_alpha_adjust[i]; } keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology); diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 817d6ce7eb9..d17ab1dc7b8 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -390,7 +390,7 @@ struct radv_pipeline_key { uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS]; uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS]; uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS]; - uint64_t vertex_alpha_adjust; + enum ac_fetch_format vertex_alpha_adjust[MAX_VERTEX_ATTRIBS]; uint32_t vertex_post_shuffle; unsigned tess_input_vertices; uint32_t col_format; diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 87288b09d5a..0e024cf2cdf 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -29,6 +29,8 @@ #define RADV_SHADER_H #include "ac_binary.h" +#include "ac_shader_util.h" + #include "amd_family.h" #include "radv_constants.h" @@ -48,13 +50,6 @@ struct radv_shader_module { char data[0]; }; -enum { - RADV_ALPHA_ADJUST_NONE = 0, - RADV_ALPHA_ADJUST_SNORM = 1, - RADV_ALPHA_ADJUST_SINT = 2, - RADV_ALPHA_ADJUST_SSCALED = 3, -}; - struct radv_vs_out_key { uint32_t as_es:1; uint32_t as_ls:1; @@ -78,7 +73,7 @@ struct radv_vs_variant_key { /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW. * so we may need to fix it up. */ - uint64_t alpha_adjust; + enum ac_fetch_format alpha_adjust[MAX_VERTEX_ATTRIBS]; /* For some formats the channels have to be shuffled. */ uint32_t post_shuffle;