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radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*
The registers don't exist on GFX9. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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de7967a27a
commit
b054718218
1 changed files with 19 additions and 15 deletions
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@ -4081,24 +4081,28 @@ static void si_init_config(struct si_context *sctx)
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raster_config_1 = 0x00000000;
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break;
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default:
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fprintf(stderr,
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"radeonsi: Unknown GPU, using 0 for raster_config\n");
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raster_config = 0x00000000;
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raster_config_1 = 0x00000000;
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if (sctx->b.chip_class <= VI) {
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fprintf(stderr,
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"radeonsi: Unknown GPU, using 0 for raster_config\n");
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raster_config = 0x00000000;
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raster_config_1 = 0x00000000;
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}
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break;
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}
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/* Always use the default config when all backends are enabled
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* (or when we failed to determine the enabled backends).
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*/
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if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
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si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
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raster_config);
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if (sctx->b.chip_class >= CIK)
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si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
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raster_config_1);
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} else {
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si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
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if (sctx->b.chip_class <= VI) {
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if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
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/* Always use the default config when all backends are enabled
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* (or when we failed to determine the enabled backends).
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*/
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si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
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raster_config);
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if (sctx->b.chip_class >= CIK)
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si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
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raster_config_1);
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} else {
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si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
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}
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}
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si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
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