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i965: Emit the depth/stencil state pointer directly, not via atoms.

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See two commits ago for the rationale.  This allows us to delete the
whole gen7_cc_state.c file.

This does move these commands before the depth stall flushes from
brw_emit_depthbuffer, which may be a problem.  The documentation for
3DSTATE_DEPTH_BUFFER mentions that depth stall flushes are required
before changing any depth/stencil buffer state, but explicitly lists
3DSTATE_DEPTH_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER,
and 3DSTATE_CLEAR_PARAMS.  It does not mention this particular packet
(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS).

No observed Piglit regressions on Sandybridge or Ivybridge.

Together with the last two commits, this makes a cairo-gl benchmark
faster by 0.324552% +/- 0.258355% on Ivybridge.  No statistically
significant change on Sandybridge.  (Thanks to Eric for the numbers.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Kenneth Graunke 2013-06-08 13:20:43 -07:00
parent 8ab15bacf4
commit b00d61151d
7 changed files with 18 additions and 80 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/mesa/drivers/dri/i965/Makefile.sources
View file

@ -114,7 +114,6 @@ i965_FILES = \
gen6_vs_state.c \
gen6_wm_state.c \
gen7_blorp.cpp \
gen7_cc_state.c \
gen7_clip_state.c \
gen7_disable.c \
gen7_misc_state.c \

2
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -606,7 +606,6 @@ struct brw_vs_prog_data {
#define SHADER_TIME_STRIDE 64
enum brw_cache_id {
BRW_DEPTH_STENCIL_STATE,
BRW_CC_VP,
BRW_CC_UNIT,
BRW_WM_PROG,
@ -699,7 +698,6 @@ enum shader_time_shader_type {
/* Flags for brw->state.cache.
*/
#define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
#define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
#define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
#define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)

1
src/mesa/drivers/dri/i965/brw_state.h
View file

@ -108,7 +108,6 @@ extern const struct brw_tracked_state gen6_wm_state;
extern const struct brw_tracked_state gen7_depthbuffer;
extern const struct brw_tracked_state gen7_cc_viewport_state_pointer;
extern const struct brw_tracked_state gen7_clip_state;
extern const struct brw_tracked_state gen7_depth_stencil_state_pointer;
extern const struct brw_tracked_state gen7_disable_stages;
extern const struct brw_tracked_state gen7_ps_state;
extern const struct brw_tracked_state gen7_samplers;

3
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -122,7 +122,6 @@ static const struct brw_tracked_state *gen6_atoms[] =
&gen6_blend_state, /* must do before cc unit */
&gen6_color_calc_state, /* must do before cc unit */
&gen6_depth_stencil_state, /* must do before cc unit */
&gen6_cc_state_pointers,
&gen6_vs_push_constants, /* Before vs_state */
&gen6_wm_push_constants, /* Before wm_state */
@ -188,7 +187,6 @@ static const struct brw_tracked_state *gen7_atoms[] =
&gen6_blend_state, /* must do before cc unit */
&gen6_color_calc_state, /* must do before cc unit */
&gen6_depth_stencil_state, /* must do before cc unit */
&gen7_depth_stencil_state_pointer,
&gen6_vs_push_constants, /* Before vs_state */
&gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
@ -392,7 +390,6 @@ static struct dirty_bit_map brw_bits[] = {
};
static struct dirty_bit_map cache_bits[] = {
DEFINE_BIT(CACHE_NEW_DEPTH_STENCIL_STATE),
DEFINE_BIT(CACHE_NEW_CC_VP),
DEFINE_BIT(CACHE_NEW_CC_UNIT),
DEFINE_BIT(CACHE_NEW_WM_PROG),

22
src/mesa/drivers/dri/i965/gen6_cc.c
View file

@ -300,25 +300,3 @@ const struct brw_tracked_state gen6_color_calc_state = {
},
.emit = gen6_upload_color_calc_state,
};
static void upload_cc_state_pointers(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
OUT_BATCH(0);
ADVANCE_BATCH();
}
const struct brw_tracked_state gen6_cc_state_pointers = {
.dirty = {
.mesa = 0,
.brw = (BRW_NEW_BATCH |
BRW_NEW_STATE_BASE_ADDRESS),
.cache = CACHE_NEW_DEPTH_STENCIL_STATE
},
.emit = upload_cc_state_pointers,
};

20
src/mesa/drivers/dri/i965/gen6_depthstencil.c
View file

@ -25,14 +25,17 @@
*
*/
#include "intel_batchbuffer.h"
#include "intel_fbo.h"
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_state.h"
static void
gen6_upload_depth_stencil_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->intel.ctx;
struct intel_context *intel = &brw->intel;
struct gen6_depth_stencil_state *ds;
struct intel_renderbuffer *depth_irb;
@ -84,13 +87,26 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
ds->ds2.depth_write_enable = ctx->Depth.Mask;
}
brw->state.dirty.cache |= CACHE_NEW_DEPTH_STENCIL_STATE;
/* Point the GPU at the new indirect state. */
if (intel->gen == 6) {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
ADVANCE_BATCH();
}
}
const struct brw_tracked_state gen6_depth_stencil_state = {
.dirty = {
.mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS,
.brw = BRW_NEW_BATCH,
.brw = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS,
.cache = 0,
},
.emit = gen6_upload_depth_stencil_state,

49
src/mesa/drivers/dri/i965/gen7_cc_state.c
View file

@ -1,49 +0,0 @@
/*
* Copyright © 2011 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
#include "brw_util.h"
#include "intel_batchbuffer.h"
#include "main/macros.h"
static void
upload_depth_stencil_state_pointer(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
ADVANCE_BATCH();
}
const struct brw_tracked_state gen7_depth_stencil_state_pointer = {
.dirty = {
.mesa = 0,
.brw = BRW_NEW_BATCH,
.cache = CACHE_NEW_DEPTH_STENCIL_STATE
},
.emit = upload_depth_stencil_state_pointer,
};