diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index c3650df960c..62c2c1f5e5f 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -1691,6 +1691,8 @@ brw_allocate_registers(fs_visitor &s, bool allow_spilling)
 
    s.debug_optimizer(nir, "lowered_vgrfs_to_fixed_grfs", 96, 3);
 
+   brw_shader_phase_update(s, BRW_SHADER_PHASE_AFTER_REGALLOC);
+
    if (s.last_scratch > 0) {
       /* We currently only support up to 2MB of scratch space.  If we
        * need to support more eventually, the documentation suggests
@@ -1876,6 +1878,14 @@ brw_cs_get_dispatch_info(const struct intel_device_info *devinfo,
    return info;
 }
 
+void
+brw_shader_phase_update(fs_visitor &s, enum brw_shader_phase phase)
+{
+   assert(phase == s.phase + 1);
+   s.phase = phase;
+   brw_fs_validate(s);
+}
+
 bool brw_should_print_shader(const nir_shader *shader, uint64_t debug_flag)
 {
    return INTEL_DEBUG(debug_flag) && (!shader->info.internal || NIR_DEBUG(PRINT_INTERNAL));
diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index 4d6e12937f0..a10d200f76a 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -257,6 +257,16 @@ enum instruction_scheduler_mode {
 
 class instruction_scheduler;
 
+enum brw_shader_phase {
+   BRW_SHADER_PHASE_INITIAL = 0,
+   BRW_SHADER_PHASE_AFTER_NIR,
+   BRW_SHADER_PHASE_AFTER_OPT_LOOP,
+   BRW_SHADER_PHASE_AFTER_EARLY_LOWERING,
+   BRW_SHADER_PHASE_AFTER_MIDDLE_LOWERING,
+   BRW_SHADER_PHASE_AFTER_LATE_LOWERING,
+   BRW_SHADER_PHASE_AFTER_REGALLOC,
+};
+
 /**
  * The fragment shader front-end.
  *
@@ -365,6 +375,8 @@ public:
    brw_reg dual_src_output;
    int first_non_payload_grf;
 
+   enum brw_shader_phase phase;
+
    bool failed;
    char *fail_msg;
 
@@ -594,6 +606,8 @@ int brw_get_subgroup_id_param_index(const intel_device_info *devinfo,
 
 void nir_to_brw(fs_visitor *s);
 
+void brw_shader_phase_update(fs_visitor &s, enum brw_shader_phase phase);
+
 #ifndef NDEBUG
 void brw_fs_validate(const fs_visitor &s);
 #else
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 2ab59810ae3..c880997a4dc 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -8432,4 +8432,6 @@ nir_to_brw(fs_visitor *s)
    ntb.bld.emit(SHADER_OPCODE_HALT_TARGET);
 
    ralloc_free(ntb.mem_ctx);
+
+   brw_shader_phase_update(*s, BRW_SHADER_PHASE_AFTER_NIR);
 }
diff --git a/src/intel/compiler/brw_fs_opt.cpp b/src/intel/compiler/brw_fs_opt.cpp
index 9537c84d6f3..9e969be1b72 100644
--- a/src/intel/compiler/brw_fs_opt.cpp
+++ b/src/intel/compiler/brw_fs_opt.cpp
@@ -80,6 +80,8 @@ brw_fs_optimize(fs_visitor &s)
       OPT(brw_fs_opt_compact_virtual_grfs);
    } while (progress);
 
+   brw_shader_phase_update(s, BRW_SHADER_PHASE_AFTER_OPT_LOOP);
+
    progress = false;
    pass_num = 0;
 
@@ -93,6 +95,8 @@ brw_fs_optimize(fs_visitor &s)
    OPT(brw_fs_lower_barycentrics);
    OPT(brw_fs_lower_logical_sends);
 
+   brw_shader_phase_update(s, BRW_SHADER_PHASE_AFTER_EARLY_LOWERING);
+
    /* After logical SEND lowering. */
 
    if (OPT(brw_fs_opt_copy_propagation_defs) || OPT(brw_fs_opt_copy_propagation))
@@ -131,6 +135,8 @@ brw_fs_optimize(fs_visitor &s)
       OPT(brw_fs_opt_dead_code_eliminate);
    }
 
+   brw_shader_phase_update(s, BRW_SHADER_PHASE_AFTER_MIDDLE_LOWERING);
+
    OPT(brw_fs_lower_alu_restrictions);
 
    OPT(brw_fs_opt_combine_constants);
@@ -169,6 +175,8 @@ brw_fs_optimize(fs_visitor &s)
    OPT(brw_fs_lower_find_live_channel);
 
    OPT(brw_fs_lower_load_subgroup_invocation);
+
+   brw_shader_phase_update(s, BRW_SHADER_PHASE_AFTER_LATE_LOWERING);
 }
 
 static unsigned
diff --git a/src/intel/compiler/brw_fs_validate.cpp b/src/intel/compiler/brw_fs_validate.cpp
index 60aff9ec04f..05e6729da04 100644
--- a/src/intel/compiler/brw_fs_validate.cpp
+++ b/src/intel/compiler/brw_fs_validate.cpp
@@ -179,6 +179,9 @@ brw_fs_validate(const fs_visitor &s)
 {
    const intel_device_info *devinfo = s.devinfo;
 
+   if (s.phase <= BRW_SHADER_PHASE_AFTER_NIR)
+      return;
+
    s.cfg->validate(_mesa_shader_stage_to_abbrev(s.stage));
 
    foreach_block_and_inst (block, fs_inst, inst, s.cfg) {
diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp
index 666f106d9bc..ca1544058ce 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -470,6 +470,8 @@ fs_visitor::init()
 
    this->grf_used = 0;
    this->spilled_any_registers = false;
+
+   this->phase = BRW_SHADER_PHASE_INITIAL;
 }
 
 fs_visitor::~fs_visitor()