diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c
index 5fc818fe83b..f2f9d14b67c 100644
--- a/src/gallium/drivers/iris/iris_batch.c
+++ b/src/gallium/drivers/iris/iris_batch.c
@@ -234,7 +234,7 @@ iris_init_batch(struct iris_context *ice,
          INTEL_BATCH_DECODE_FLOATS;
 
       intel_batch_decode_ctx_init(&batch->decoder, &screen->compiler->isa,
-                                  &screen->devinfo,
+                                  screen->devinfo,
                                   stderr, decode_flags, NULL,
                                   decode_get_bo, decode_get_state_size, batch);
       batch->decoder.dynamic_base = IRIS_MEMZONE_DYNAMIC_START;
@@ -272,7 +272,7 @@ static int
 iris_create_engines_context(struct iris_context *ice, int priority)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    int fd = iris_bufmgr_get_fd(screen->bufmgr);
 
    struct intel_query_engine_info *engines_info = intel_engine_get_info(fd);
@@ -518,7 +518,7 @@ iris_batch_reset(struct iris_batch *batch)
 {
    struct iris_screen *screen = batch->screen;
    struct iris_bufmgr *bufmgr = screen->bufmgr;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    u_trace_fini(&batch->trace);
 
@@ -687,7 +687,7 @@ finish_seqno(struct iris_batch *batch)
 static void
 iris_finish_batch(struct iris_batch *batch)
 {
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    if (devinfo->ver == 12 && batch->name == IRIS_BATCH_RENDER) {
       /* We re-emit constants at the beginning of every batch as a hardware
@@ -981,7 +981,7 @@ submit_batch(struct iris_batch *batch)
    }
 
    int ret = 0;
-   if (!batch->screen->devinfo.no_hw &&
+   if (!batch->screen->devinfo->no_hw &&
        intel_ioctl(batch->screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf))
       ret = -errno;
 
diff --git a/src/gallium/drivers/iris/iris_batch.h b/src/gallium/drivers/iris/iris_batch.h
index 8b4162eabe1..a03d6bb3d89 100644
--- a/src/gallium/drivers/iris/iris_batch.h
+++ b/src/gallium/drivers/iris/iris_batch.h
@@ -357,7 +357,7 @@ static inline void
 iris_batch_mark_flush_sync(struct iris_batch *batch,
                            enum iris_domain access)
 {
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    if (iris_domain_is_l3_coherent(devinfo, access))
       batch->l3_coherent_seqnos[access] = batch->next_seqno - 1;
@@ -374,7 +374,7 @@ static inline void
 iris_batch_mark_invalidate_sync(struct iris_batch *batch,
                                 enum iris_domain access)
 {
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    for (unsigned i = 0; i < NUM_IRIS_DOMAINS; i++) {
       if (i == access)
@@ -428,7 +428,7 @@ iris_batch_name_to_string(enum iris_batch_name name);
 
 #define iris_foreach_batch(ice, batch)                \
    for (struct iris_batch *batch = &ice->batches[0];  \
-        batch <= &ice->batches[((struct iris_screen *)ice->ctx.screen)->devinfo.ver >= 12 ? IRIS_BATCH_BLITTER : IRIS_BATCH_COMPUTE]; \
+        batch <= &ice->batches[((struct iris_screen *)ice->ctx.screen)->devinfo->ver >= 12 ? IRIS_BATCH_BLITTER : IRIS_BATCH_COMPUTE]; \
         ++batch)
 
 #endif
diff --git a/src/gallium/drivers/iris/iris_binder.c b/src/gallium/drivers/iris/iris_binder.c
index 511b9725096..97489e3aa13 100644
--- a/src/gallium/drivers/iris/iris_binder.c
+++ b/src/gallium/drivers/iris/iris_binder.c
@@ -205,7 +205,7 @@ void
 iris_init_binder(struct iris_context *ice)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    memset(&ice->state.binder, 0, sizeof(struct iris_binder));
 
diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c
index ea9fc9875d3..a6a798ad4eb 100644
--- a/src/gallium/drivers/iris/iris_blit.c
+++ b/src/gallium/drivers/iris/iris_blit.c
@@ -288,7 +288,7 @@ tex_cache_flush_hack(struct iris_batch *batch,
                      enum isl_format view_format,
                      enum isl_format surf_format)
 {
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    /* The WaSamplerCacheFlushBetweenRedescribedSurfaceReads workaround says:
     *
@@ -365,7 +365,7 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
 {
    struct iris_context *ice = (void *) ctx;
    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
    enum blorp_batch_flags blorp_flags = iris_blorp_flags_for_batch(batch);
 
@@ -573,7 +573,7 @@ get_copy_region_aux_settings(struct iris_context *ice,
                              bool is_dest)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    switch (res->aux.usage) {
    case ISL_AUX_USAGE_HIZ:
diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c
index c6fc65e437f..8c96272d581 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.c
+++ b/src/gallium/drivers/iris/iris_bufmgr.c
@@ -231,6 +231,7 @@ struct iris_bufmgr {
 
    int next_screen_id;
 
+   struct intel_device_info devinfo;
    bool has_llc:1;
    bool has_local_mem:1;
    bool has_mmap_offset:1;
@@ -2405,6 +2406,8 @@ iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse)
 
    list_inithead(&bufmgr->zombie_list);
 
+   bufmgr->devinfo = *devinfo;
+   devinfo = &bufmgr->devinfo;
    bufmgr->has_llc = devinfo->has_llc;
    bufmgr->has_local_mem = devinfo->has_local_mem;
    bufmgr->has_caching_uapi = devinfo->has_caching_uapi;
@@ -2599,3 +2602,9 @@ iris_bufmgr_sram_size(struct iris_bufmgr *bufmgr)
 {
    return bufmgr->sys.size;
 }
+
+const struct intel_device_info *
+iris_bufmgr_get_device_info(struct iris_bufmgr *bufmgr)
+{
+   return &bufmgr->devinfo;
+}
diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h
index 68a1c989cf2..a13ad725829 100644
--- a/src/gallium/drivers/iris/iris_bufmgr.h
+++ b/src/gallium/drivers/iris/iris_bufmgr.h
@@ -601,5 +601,6 @@ uint32_t iris_upload_border_color(struct iris_border_color_pool *pool,
 
 uint64_t iris_bufmgr_vram_size(struct iris_bufmgr *bufmgr);
 uint64_t iris_bufmgr_sram_size(struct iris_bufmgr *bufmgr);
+const struct intel_device_info *iris_bufmgr_get_device_info(struct iris_bufmgr *bufmgr);
 
 #endif /* IRIS_BUFMGR_H */
diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c
index 300d5768f68..253a04a2be0 100644
--- a/src/gallium/drivers/iris/iris_clear.c
+++ b/src/gallium/drivers/iris/iris_clear.c
@@ -41,7 +41,7 @@ iris_is_color_fast_clear_compatible(struct iris_context *ice,
                                     const union isl_color_value color)
 {
    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    if (isl_format_has_int_channel(format)) {
       perf_debug(&ice->dbg, "Integer fast clear not enabled for %s\n",
@@ -168,7 +168,7 @@ fast_clear_color(struct iris_context *ice,
                  union isl_color_value color)
 {
    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
    struct pipe_resource *p_res = (void *) res;
 
    bool color_changed = res->aux.clear_color_unknown ||
@@ -315,7 +315,7 @@ clear_color(struct iris_context *ice,
    struct iris_resource *res = (void *) p_res;
 
    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
    enum blorp_batch_flags blorp_flags = iris_blorp_flags_for_batch(batch);
 
    if (render_condition_enabled) {
@@ -384,7 +384,7 @@ can_fast_clear_depth(struct iris_context *ice,
    struct pipe_resource *p_res = (void *) res;
    struct pipe_context *ctx = (void *) ice;
    struct iris_screen *screen = (void *) ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
       return false;
@@ -677,7 +677,7 @@ iris_clear_texture(struct pipe_context *ctx,
 {
    struct iris_context *ice = (void *) ctx;
    struct iris_screen *screen = (void *) ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    if (util_format_is_depth_or_stencil(p_res->format)) {
       const struct util_format_unpack_description *unpack =
diff --git a/src/gallium/drivers/iris/iris_context.c b/src/gallium/drivers/iris/iris_context.c
index 47d1e023b4a..a9dcf73e92c 100644
--- a/src/gallium/drivers/iris/iris_context.c
+++ b/src/gallium/drivers/iris/iris_context.c
@@ -288,7 +288,7 @@ struct pipe_context *
 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
 {
    struct iris_screen *screen = (struct iris_screen*)pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_context *ice = rzalloc(NULL, struct iris_context);
 
    if (!ice)
diff --git a/src/gallium/drivers/iris/iris_disk_cache.c b/src/gallium/drivers/iris/iris_disk_cache.c
index 777d9e8a327..24ad475b1f9 100644
--- a/src/gallium/drivers/iris/iris_disk_cache.c
+++ b/src/gallium/drivers/iris/iris_disk_cache.c
@@ -268,7 +268,7 @@ iris_disk_cache_init(struct iris_screen *screen)
    /* array length = print length + nul char + 1 extra to verify it's unused */
    char renderer[11];
    UNUSED int len =
-      snprintf(renderer, sizeof(renderer), "iris_%04x", screen->devinfo.pci_device_id);
+      snprintf(renderer, sizeof(renderer), "iris_%04x", screen->devinfo->pci_device_id);
    assert(len == sizeof(renderer) - 2);
 
    const struct build_id_note *note =
diff --git a/src/gallium/drivers/iris/iris_draw.c b/src/gallium/drivers/iris/iris_draw.c
index 88ee1f6b9ed..de4e834b993 100644
--- a/src/gallium/drivers/iris/iris_draw.c
+++ b/src/gallium/drivers/iris/iris_draw.c
@@ -66,7 +66,7 @@ iris_update_draw_info(struct iris_context *ice,
                       const struct pipe_draw_info *info)
 {
    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    const struct brw_compiler *compiler = screen->compiler;
 
    if (ice->state.prim_mode != info->mode) {
@@ -270,7 +270,7 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info,
 
    struct iris_context *ice = (struct iris_context *) ctx;
    struct iris_screen *screen = (struct iris_screen*)ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
 
    if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
@@ -383,7 +383,7 @@ iris_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info *grid)
 {
    struct iris_context *ice = (struct iris_context *) ctx;
    struct iris_screen *screen = (struct iris_screen *) ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_batch *batch = &ice->batches[IRIS_BATCH_COMPUTE];
 
    if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
diff --git a/src/gallium/drivers/iris/iris_formats.c b/src/gallium/drivers/iris/iris_formats.c
index 0e846532e78..01cc3c2d871 100644
--- a/src/gallium/drivers/iris/iris_formats.c
+++ b/src/gallium/drivers/iris/iris_formats.c
@@ -111,7 +111,7 @@ iris_is_format_supported(struct pipe_screen *pscreen,
                          unsigned usage)
 {
    struct iris_screen *screen = (struct iris_screen *) pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    uint32_t max_samples = devinfo->ver == 8 ? 8 : 16;
 
    if (sample_count > max_samples ||
diff --git a/src/gallium/drivers/iris/iris_measure.c b/src/gallium/drivers/iris/iris_measure.c
index ec05be8882f..227e1ebb796 100644
--- a/src/gallium/drivers/iris/iris_measure.c
+++ b/src/gallium/drivers/iris/iris_measure.c
@@ -340,7 +340,7 @@ iris_destroy_ctx_measure(struct iris_context *ice)
     * destroyed.
     */
    struct iris_screen *screen = (struct iris_screen *) ice->ctx.screen;
-   intel_measure_gather(&screen->measure, &screen->devinfo);
+   intel_measure_gather(&screen->measure, screen->devinfo);
 }
 
 void
@@ -383,7 +383,7 @@ iris_measure_batch_end(struct iris_context *ice, struct iris_batch *batch)
 
    static int interval = 0;
    if (++interval > 10) {
-      intel_measure_gather(measure_device, &screen->devinfo);
+      intel_measure_gather(measure_device, screen->devinfo);
       interval = 0;
    }
 }
@@ -401,5 +401,5 @@ iris_measure_frame_end(struct iris_context *ice)
    /* increment frame counter */
    intel_measure_frame_transition(p_atomic_inc_return(&measure_device->frame));
 
-   intel_measure_gather(measure_device, &screen->devinfo);
+   intel_measure_gather(measure_device, screen->devinfo);
 }
diff --git a/src/gallium/drivers/iris/iris_monitor.c b/src/gallium/drivers/iris/iris_monitor.c
index f24db9bef41..c4ed85e8397 100644
--- a/src/gallium/drivers/iris/iris_monitor.c
+++ b/src/gallium/drivers/iris/iris_monitor.c
@@ -114,7 +114,7 @@ iris_monitor_init_metrics(struct iris_screen *screen)
 
    iris_perf_init_vtbl(perf_cfg);
 
-   intel_perf_init_metrics(perf_cfg, &screen->devinfo, screen->fd,
+   intel_perf_init_metrics(perf_cfg, screen->devinfo, screen->fd,
                            true /* pipeline stats*/,
                            true /* register snapshots */);
 
@@ -169,7 +169,7 @@ iris_init_monitor_ctx(struct iris_context *ice)
                          ice,
                          ice,
                          screen->bufmgr,
-                         &screen->devinfo,
+                         screen->devinfo,
                          ice->batches[IRIS_BATCH_RENDER].ctx_id,
                          screen->fd);
 }
diff --git a/src/gallium/drivers/iris/iris_performance_query.c b/src/gallium/drivers/iris/iris_performance_query.c
index 5f19878a7fa..232af86982a 100644
--- a/src/gallium/drivers/iris/iris_performance_query.c
+++ b/src/gallium/drivers/iris/iris_performance_query.c
@@ -68,7 +68,7 @@ iris_init_perf_query_info(struct pipe_context *pipe)
 
    iris_perf_init_vtbl(perf_cfg);
 
-   intel_perf_init_metrics(perf_cfg, &screen->devinfo, screen->fd,
+   intel_perf_init_metrics(perf_cfg, screen->devinfo, screen->fd,
                            true /* pipeline_statistics */,
                            true /* register snapshots */);
 
@@ -77,7 +77,7 @@ iris_init_perf_query_info(struct pipe_context *pipe)
                          ice,
                          ice,
                          screen->bufmgr,
-                         &screen->devinfo,
+                         screen->devinfo,
                          ice->batches[IRIS_BATCH_RENDER].ctx_id,
                          screen->fd);
 
diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c
index 4050f8641b0..f26d853ae37 100644
--- a/src/gallium/drivers/iris/iris_pipe_control.c
+++ b/src/gallium/drivers/iris/iris_pipe_control.c
@@ -184,7 +184,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
                              struct iris_bo *bo,
                              enum iris_domain access)
 {
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
    const struct brw_compiler *compiler = batch->screen->compiler;
 
    const bool access_via_l3 = iris_domain_is_l3_coherent(devinfo, access);
diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c
index 4df3b877579..31330bc57fd 100644
--- a/src/gallium/drivers/iris/iris_program.c
+++ b/src/gallium/drivers/iris/iris_program.c
@@ -100,7 +100,7 @@ iris_to_brw_vs_key(const struct iris_screen *screen,
                    const struct iris_vs_prog_key *key)
 {
    return (struct brw_vs_prog_key) {
-      BRW_KEY_INIT(screen->devinfo.ver, key->vue.base.program_string_id,
+      BRW_KEY_INIT(screen->devinfo->ver, key->vue.base.program_string_id,
                    key->vue.base.limit_trig_input_range),
 
       /* Don't tell the backend about our clip plane constants, we've
@@ -115,7 +115,7 @@ iris_to_brw_tcs_key(const struct iris_screen *screen,
                     const struct iris_tcs_prog_key *key)
 {
    return (struct brw_tcs_prog_key) {
-      BRW_KEY_INIT(screen->devinfo.ver, key->vue.base.program_string_id,
+      BRW_KEY_INIT(screen->devinfo->ver, key->vue.base.program_string_id,
                    key->vue.base.limit_trig_input_range),
       ._tes_primitive_mode = key->_tes_primitive_mode,
       .input_vertices = key->input_vertices,
@@ -130,7 +130,7 @@ iris_to_brw_tes_key(const struct iris_screen *screen,
                     const struct iris_tes_prog_key *key)
 {
    return (struct brw_tes_prog_key) {
-      BRW_KEY_INIT(screen->devinfo.ver, key->vue.base.program_string_id,
+      BRW_KEY_INIT(screen->devinfo->ver, key->vue.base.program_string_id,
                    key->vue.base.limit_trig_input_range),
       .patch_inputs_read = key->patch_inputs_read,
       .inputs_read = key->inputs_read,
@@ -142,7 +142,7 @@ iris_to_brw_gs_key(const struct iris_screen *screen,
                    const struct iris_gs_prog_key *key)
 {
    return (struct brw_gs_prog_key) {
-      BRW_KEY_INIT(screen->devinfo.ver, key->vue.base.program_string_id,
+      BRW_KEY_INIT(screen->devinfo->ver, key->vue.base.program_string_id,
                    key->vue.base.limit_trig_input_range),
    };
 }
@@ -152,7 +152,7 @@ iris_to_brw_fs_key(const struct iris_screen *screen,
                    const struct iris_fs_prog_key *key)
 {
    return (struct brw_wm_prog_key) {
-      BRW_KEY_INIT(screen->devinfo.ver, key->base.program_string_id,
+      BRW_KEY_INIT(screen->devinfo->ver, key->base.program_string_id,
                    key->base.limit_trig_input_range),
       .nr_color_regions = key->nr_color_regions,
       .flat_shade = key->flat_shade,
@@ -174,7 +174,7 @@ iris_to_brw_cs_key(const struct iris_screen *screen,
                    const struct iris_cs_prog_key *key)
 {
    return (struct brw_cs_prog_key) {
-      BRW_KEY_INIT(screen->devinfo.ver, key->base.program_string_id,
+      BRW_KEY_INIT(screen->devinfo->ver, key->base.program_string_id,
                    key->base.limit_trig_input_range),
    };
 }
@@ -1326,7 +1326,7 @@ iris_compile_vs(struct iris_screen *screen,
                 struct iris_compiled_shader *shader)
 {
    const struct brw_compiler *compiler = screen->compiler;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    void *mem_ctx = ralloc_context(NULL);
    struct brw_vs_prog_data *vs_prog_data =
       rzalloc(mem_ctx, struct brw_vs_prog_data);
@@ -1511,7 +1511,7 @@ iris_compile_tcs(struct iris_screen *screen,
       rzalloc(mem_ctx, struct brw_tcs_prog_data);
    struct brw_vue_prog_data *vue_prog_data = &tcs_prog_data->base;
    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    enum brw_param_builtin *system_values = NULL;
    unsigned num_system_values = 0;
    unsigned num_cbufs = 0;
@@ -1617,7 +1617,7 @@ iris_update_compiled_tcs(struct iris_context *ice)
    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
    struct u_upload_mgr *uploader = ice->shaders.uploader_driver;
    const struct brw_compiler *compiler = screen->compiler;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    const struct shader_info *tes_info =
       iris_get_shader_info(ice, MESA_SHADER_TESS_EVAL);
@@ -1699,7 +1699,7 @@ iris_compile_tes(struct iris_screen *screen,
    struct brw_vue_prog_data *vue_prog_data = &tes_prog_data->base;
    struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
    enum brw_param_builtin *system_values;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    unsigned num_system_values;
    unsigned num_cbufs;
 
@@ -1832,7 +1832,7 @@ iris_compile_gs(struct iris_screen *screen,
                 struct iris_compiled_shader *shader)
 {
    const struct brw_compiler *compiler = screen->compiler;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    void *mem_ctx = ralloc_context(NULL);
    struct brw_gs_prog_data *gs_prog_data =
       rzalloc(mem_ctx, struct brw_gs_prog_data);
@@ -1972,7 +1972,7 @@ iris_compile_fs(struct iris_screen *screen,
       rzalloc(mem_ctx, struct brw_wm_prog_data);
    struct brw_stage_prog_data *prog_data = &fs_prog_data->base;
    enum brw_param_builtin *system_values;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    unsigned num_system_values;
    unsigned num_cbufs;
 
@@ -2264,7 +2264,7 @@ iris_compile_cs(struct iris_screen *screen,
       rzalloc(mem_ctx, struct brw_cs_prog_data);
    struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
    enum brw_param_builtin *system_values;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    unsigned num_system_values;
    unsigned num_cbufs;
 
@@ -2384,7 +2384,7 @@ iris_get_scratch_space(struct iris_context *ice,
 {
    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
    struct iris_bufmgr *bufmgr = screen->bufmgr;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    unsigned encoded_size = ffs(per_thread_scratch) - 11;
    assert(encoded_size < ARRAY_SIZE(ice->shaders.scratch_bos));
@@ -2415,7 +2415,7 @@ iris_get_scratch_surf(struct iris_context *ice,
                       unsigned per_thread_scratch)
 {
    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
-   ASSERTED const struct intel_device_info *devinfo = &screen->devinfo;
+   ASSERTED const struct intel_device_info *devinfo = screen->devinfo;
 
    assert(devinfo->verx10 >= 125);
 
@@ -2690,7 +2690,7 @@ iris_create_shader_state(struct pipe_context *ctx,
       bool can_rearrange_varyings =
          util_bitcount64(info->inputs_read & BRW_FS_VARYING_INPUT_MASK) <= 16;
 
-      const struct intel_device_info *devinfo = &screen->devinfo;
+      const struct intel_device_info *devinfo = screen->devinfo;
 
       key.fs = (struct iris_fs_prog_key) {
          KEY_INIT(base),
@@ -2877,7 +2877,7 @@ iris_bind_tes_state(struct pipe_context *ctx, void *state)
 {
    struct iris_context *ice = (struct iris_context *)ctx;
    struct iris_screen *screen = (struct iris_screen *) ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    /* Enabling/disabling optional stages requires a URB reconfiguration. */
    if (!!state != !!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL])
@@ -2904,7 +2904,7 @@ iris_bind_fs_state(struct pipe_context *ctx, void *state)
 {
    struct iris_context *ice = (struct iris_context *) ctx;
    struct iris_screen *screen = (struct iris_screen *) ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_uncompiled_shader *old_ish =
       ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
    struct iris_uncompiled_shader *new_ish = state;
@@ -2936,7 +2936,7 @@ iris_finalize_nir(struct pipe_screen *_screen, void *nirptr)
 {
    struct iris_screen *screen = (struct iris_screen *)_screen;
    struct nir_shader *nir = (struct nir_shader *) nirptr;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    NIR_PASS_V(nir, iris_fix_edge_flags);
 
diff --git a/src/gallium/drivers/iris/iris_program_cache.c b/src/gallium/drivers/iris/iris_program_cache.c
index a523c5bb2f2..b5cdc7279f3 100644
--- a/src/gallium/drivers/iris/iris_program_cache.c
+++ b/src/gallium/drivers/iris/iris_program_cache.c
@@ -157,7 +157,7 @@ iris_upload_shader(struct iris_screen *screen,
                    const void *key,
                    const void *assembly)
 {
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    u_upload_alloc(uploader, 0, shader->prog_data->program_size, 64,
                   &shader->assembly.offset, &shader->assembly.res,
diff --git a/src/gallium/drivers/iris/iris_query.c b/src/gallium/drivers/iris/iris_query.c
index 1af861ca7a3..f03d24fcb21 100644
--- a/src/gallium/drivers/iris/iris_query.c
+++ b/src/gallium/drivers/iris/iris_query.c
@@ -156,7 +156,7 @@ iris_pipelined_write(struct iris_batch *batch,
                      enum pipe_control_flags flags,
                      unsigned offset)
 {
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
    const unsigned optional_cs_stall =
       GFX_VER == 9 && devinfo->gt == 4 ?  PIPE_CONTROL_CS_STALL : 0;
    struct iris_bo *bo = iris_resource_bo(q->query_state_ref.res);
@@ -590,7 +590,7 @@ static void
 iris_check_query_no_flush(struct iris_context *ice, struct iris_query *q)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    if (!q->ready && READ_ONCE(q->map->snapshots_landed)) {
       calculate_result_on_cpu(devinfo, q);
@@ -610,9 +610,9 @@ iris_get_query_result(struct pipe_context *ctx,
       return iris_get_monitor_result(ctx, q->monitor, wait, result->batch);
 
    struct iris_screen *screen = (void *) ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
-   if (unlikely(screen->devinfo.no_hw)) {
+   if (unlikely(screen->devinfo->no_hw)) {
       result->u64 = 0;
       return true;
    }
@@ -660,7 +660,7 @@ iris_get_query_result_resource(struct pipe_context *ctx,
    struct iris_context *ice = (void *) ctx;
    struct iris_query *q = (void *) query;
    struct iris_batch *batch = &ice->batches[q->batch_idx];
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
    struct iris_resource *res = (void *) p_res;
    struct iris_bo *query_bo = iris_resource_bo(q->query_state_ref.res);
    struct iris_bo *dst_bo = iris_resource_bo(p_res);
@@ -707,7 +707,7 @@ iris_get_query_result_resource(struct pipe_context *ctx,
    bool predicated = !(flags & PIPE_QUERY_WAIT) && !q->stalled;
 
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
 
    iris_batch_sync_region_start(batch);
 
@@ -778,7 +778,7 @@ set_predicate_for_result(struct iris_context *ice,
    q->stalled = true;
 
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
 
    struct mi_value result;
 
diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c
index 082cd08931e..2e17e481c15 100644
--- a/src/gallium/drivers/iris/iris_resolve.c
+++ b/src/gallium/drivers/iris/iris_resolve.c
@@ -198,7 +198,7 @@ iris_predraw_resolve_framebuffer(struct iris_context *ice,
 {
    struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_uncompiled_shader *ish =
       ice->shaders.uncompiled[MESA_SHADER_FRAGMENT];
    const nir_shader *nir = ish->nir;
@@ -276,7 +276,7 @@ iris_postdraw_update_image_resolve_tracking(struct iris_context *ice,
                                             gl_shader_stage stage)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   ASSERTED struct intel_device_info *devinfo = &screen->devinfo;
+   ASSERTED const struct intel_device_info *devinfo = screen->devinfo;
 
    assert(devinfo->ver >= 12);
 
@@ -320,7 +320,7 @@ void
 iris_postdraw_update_resolve_tracking(struct iris_context *ice)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
 
    // XXX: front buffer drawing?
@@ -626,7 +626,7 @@ iris_hiz_exec(struct iris_context *ice,
               unsigned int num_layers, enum isl_aux_op op,
               bool update_clear_depth)
 {
-   ASSERTED struct intel_device_info *devinfo = &batch->screen->devinfo;
+   ASSERTED const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    assert(iris_resource_level_has_hiz(devinfo, res, level));
    assert(op != ISL_AUX_OP_NONE);
@@ -916,7 +916,7 @@ iris_resource_set_aux_state(struct iris_context *ice,
                             enum isl_aux_state aux_state)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   ASSERTED struct intel_device_info *devinfo = &screen->devinfo;
+   ASSERTED const struct intel_device_info *devinfo = screen->devinfo;
 
    num_layers = miptree_layer_range_length(res, level, start_layer, num_layers);
 
@@ -957,7 +957,7 @@ iris_resource_texture_aux_usage(struct iris_context *ice,
                                 unsigned num_levels)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    switch (res->aux.usage) {
    case ISL_AUX_USAGE_HIZ:
@@ -1015,7 +1015,7 @@ iris_image_view_aux_usage(struct iris_context *ice,
       return ISL_AUX_USAGE_NONE;
 
    const struct iris_screen *screen = (void *) ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_resource *res = (void *) pview->resource;
 
    const unsigned level = res->base.b.target != PIPE_BUFFER ?
@@ -1086,7 +1086,7 @@ iris_resource_prepare_texture(struct iris_context *ice,
                               uint32_t start_layer, uint32_t num_layers)
 {
    const struct iris_screen *screen = (void *) ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    enum isl_aux_usage aux_usage =
       iris_resource_texture_aux_usage(ice, res, view_format,
@@ -1139,7 +1139,7 @@ iris_resource_render_aux_usage(struct iris_context *ice,
                                bool draw_aux_disabled)
 {
    struct iris_screen *screen = (void *) ice->ctx.screen;
-   struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    if (draw_aux_disabled)
       return ISL_AUX_USAGE_NONE;
diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 5dcb5a4d0e1..75cae8ecde2 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -163,7 +163,7 @@ modifier_is_supported(const struct intel_device_info *devinfo,
 }
 
 static uint64_t
-select_best_modifier(struct intel_device_info *devinfo,
+select_best_modifier(const struct intel_device_info *devinfo,
                      const struct pipe_resource *templ,
                      const uint64_t *modifiers,
                      int count)
@@ -234,7 +234,7 @@ iris_query_dmabuf_modifiers(struct pipe_screen *pscreen,
                             int *count)
 {
    struct iris_screen *screen = (void *) pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    uint64_t all_modifiers[] = {
       DRM_FORMAT_MOD_LINEAR,
@@ -278,7 +278,7 @@ iris_is_dmabuf_modifier_supported(struct pipe_screen *pscreen,
                                   bool *external_only)
 {
    struct iris_screen *screen = (void *) pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    if (modifier_is_supported(devinfo, pfmt, 0, modifier)) {
       if (external_only)
@@ -316,7 +316,7 @@ iris_image_view_get_format(struct iris_context *ice,
                            const struct pipe_image_view *img)
 {
    struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
    enum isl_format isl_fmt =
@@ -471,7 +471,7 @@ iris_resource_alloc_flags(const struct iris_screen *screen,
                        PIPE_RESOURCE_FLAG_MAP_PERSISTENT))
       flags |= BO_ALLOC_SMEM;
 
-   if (screen->devinfo.verx10 >= 125 && isl_aux_usage_has_ccs(aux_usage)) {
+   if (screen->devinfo->verx10 >= 125 && isl_aux_usage_has_ccs(aux_usage)) {
       assert((flags & BO_ALLOC_SMEM) == 0);
       flags |= BO_ALLOC_LMEM;
    }
@@ -583,7 +583,7 @@ iris_get_aux_clear_color_state_size(struct iris_screen *screen,
     * sampler via render surface state objects.
     */
    if (isl_surf_usage_is_depth(res->surf.usage) &&
-       !iris_sample_with_depth_aux(&screen->devinfo, res))
+       !iris_sample_with_depth_aux(screen->devinfo, res))
       return 0;
 
    return screen->isl_dev.ss.clear_color_state_size;
@@ -601,7 +601,7 @@ map_aux_addresses(struct iris_screen *screen, struct iris_resource *res,
       const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
          res->aux.extra_aux.offset : res->aux.offset;
       const enum isl_format format =
-         iris_format_for_usage(&screen->devinfo, pfmt, res->surf.usage).fmt;
+         iris_format_for_usage(screen->devinfo, pfmt, res->surf.usage).fmt;
       const uint64_t format_bits =
          intel_aux_map_format_bits(res->surf.tiling, format, plane);
       intel_aux_map_add_mapping(aux_map_ctx, res->bo->address + res->offset,
@@ -674,7 +674,7 @@ iris_resource_configure_main(const struct iris_screen *screen,
    } else if (templ->usage == PIPE_USAGE_STAGING ||
               templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR)) {
       tiling_flags = ISL_TILING_LINEAR_BIT;
-   } else if (!screen->devinfo.has_tiling_uapi &&
+   } else if (!screen->devinfo->has_tiling_uapi &&
               (templ->bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED))) {
       tiling_flags = ISL_TILING_LINEAR_BIT;
    } else if (templ->bind & PIPE_BIND_SCANOUT) {
@@ -719,7 +719,7 @@ iris_resource_configure_main(const struct iris_screen *screen,
    }
 
    const enum isl_format format =
-      iris_format_for_usage(&screen->devinfo, templ->format, usage).fmt;
+      iris_format_for_usage(screen->devinfo, templ->format, usage).fmt;
 
    const struct isl_surf_init_info init_info = {
       .dim = target_to_isl_surf_dim(templ->target),
@@ -787,7 +787,7 @@ static bool
 iris_resource_configure_aux(struct iris_screen *screen,
                             struct iris_resource *res, bool imported)
 {
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    const bool has_mcs =
       isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
@@ -1153,7 +1153,7 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
                                     int modifiers_count)
 {
    struct iris_screen *screen = (struct iris_screen *)pscreen;
-   struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_resource *res = iris_alloc_resource(pscreen, templ);
 
    if (!res)
diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c
index 3ee6114b523..a6af04f73ff 100644
--- a/src/gallium/drivers/iris/iris_screen.c
+++ b/src/gallium/drivers/iris/iris_screen.c
@@ -98,14 +98,14 @@ iris_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
 {
    struct iris_screen *screen = (struct iris_screen *)pscreen;
 
-   intel_uuid_compute_device_id((uint8_t *)uuid, &screen->devinfo, PIPE_UUID_SIZE);
+   intel_uuid_compute_device_id((uint8_t *)uuid, screen->devinfo, PIPE_UUID_SIZE);
 }
 
 static void
 iris_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
 {
    struct iris_screen *screen = (struct iris_screen *)pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE);
 }
@@ -136,7 +136,7 @@ static const char *
 iris_get_name(struct pipe_screen *pscreen)
 {
    struct iris_screen *screen = (struct iris_screen *)pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    static char buf[128];
 
    snprintf(buf, sizeof(buf), "Mesa %s", devinfo->name);
@@ -147,7 +147,7 @@ static const char *
 iris_get_cl_cts_version(struct pipe_screen *pscreen)
 {
    struct iris_screen *screen = (struct iris_screen *)pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    /* https://www.khronos.org/conformance/adopters/conformant-products/opencl#submission_405 */
    if (devinfo->verx10 == 120)
@@ -172,7 +172,7 @@ iris_get_video_memory(struct iris_screen *screen)
        * We should probably never end up here. This is just a fallback to get
        * some kind of value in case os_get_available_system_memory fails.
        */
-      const struct intel_device_info *devinfo = &screen->devinfo;
+      const struct intel_device_info *devinfo = screen->devinfo;
       /* Once a batch uses more than 75% of the maximum mappable size, we
        * assume that there's some fragmentation, and we start doing extra
        * flushing, etc.  That's the big cliff apps will care about.
@@ -200,7 +200,7 @@ static int
 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 {
    struct iris_screen *screen = (struct iris_screen *)pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    switch (param) {
    case PIPE_CAP_NPOT_TEXTURES:
@@ -371,7 +371,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_VENDOR_ID:
       return 0x8086;
    case PIPE_CAP_DEVICE_ID:
-      return screen->devinfo.pci_device_id;
+      return screen->devinfo->pci_device_id;
    case PIPE_CAP_VIDEO_MEMORY:
       return iris_get_video_memory(screen);
    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
@@ -559,7 +559,7 @@ iris_get_compute_param(struct pipe_screen *pscreen,
                        void *ret)
 {
    struct iris_screen *screen = (struct iris_screen *)pscreen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    const uint32_t max_invocations =
       MIN2(1024, 32 * devinfo->max_cs_workgroup_threads);
@@ -643,7 +643,7 @@ iris_get_timestamp(struct pipe_screen *pscreen)
                                         &result))
       return 0;
 
-   result = intel_device_info_timebase_scale(&screen->devinfo, result);
+   result = intel_device_info_timebase_scale(screen->devinfo, result);
    result &= (1ull << TIMESTAMP_BITS) - 1;
 
    return result;
@@ -781,12 +781,13 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
    if (!screen)
       return NULL;
 
-   if (!intel_get_device_info_from_fd(fd, &screen->devinfo))
+   struct intel_device_info devinfo;
+   if (!intel_get_device_info_from_fd(fd, &devinfo))
       return NULL;
 
    p_atomic_set(&screen->refcount, 1);
 
-   if (screen->devinfo.ver < 8 || screen->devinfo.platform == INTEL_PLATFORM_CHV)
+   if (devinfo.ver < 8 || devinfo.platform == INTEL_PLATFORM_CHV)
       return NULL;
 
    /* Here are the i915 features we need for Iris (in chronological order) :
@@ -798,7 +799,7 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
     *
     * Checking the last feature availability will include all previous ones.
     */
-   if (!screen->devinfo.has_context_isolation) {
+   if (!devinfo.has_context_isolation) {
       debug_error("Kernel is too old (4.16+ required) or unusable for Iris.\n"
                   "Check your dmesg logs for loading failures.\n");
       return NULL;
@@ -819,10 +820,11 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
 
    brw_process_intel_debug_variable();
 
-   screen->bufmgr = iris_bufmgr_get_for_fd(&screen->devinfo, fd, bo_reuse);
+   screen->bufmgr = iris_bufmgr_get_for_fd(&devinfo, fd, bo_reuse);
    if (!screen->bufmgr)
       return NULL;
 
+   screen->devinfo = iris_bufmgr_get_device_info(screen->bufmgr);
    screen->fd = iris_bufmgr_get_fd(screen->bufmgr);
    screen->winsys_fd = os_dupfd_cloexec(fd);
 
@@ -852,16 +854,16 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
 
    screen->precompile = debug_get_bool_option("shader_precompile", true);
 
-   isl_device_init(&screen->isl_dev, &screen->devinfo);
+   isl_device_init(&screen->isl_dev, screen->devinfo);
 
-   screen->compiler = brw_compiler_create(screen, &screen->devinfo);
+   screen->compiler = brw_compiler_create(screen, screen->devinfo);
    screen->compiler->shader_debug_log = iris_shader_debug_log;
    screen->compiler->shader_perf_log = iris_shader_perf_log;
    screen->compiler->supports_shader_constants = true;
-   screen->compiler->indirect_ubos_use_sampler = screen->devinfo.ver < 12;
+   screen->compiler->indirect_ubos_use_sampler = screen->devinfo->ver < 12;
 
-   screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false);
-   screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true);
+   screen->l3_config_3d = iris_get_default_l3_config(screen->devinfo, false);
+   screen->l3_config_cs = iris_get_default_l3_config(screen->devinfo, true);
 
    iris_disk_cache_init(screen);
 
@@ -897,7 +899,7 @@ iris_screen_create(int fd, const struct pipe_screen_config *config)
    pscreen->get_driver_query_info = iris_get_monitor_info;
    iris_init_screen_program_functions(pscreen);
 
-   genX_call(&screen->devinfo, init_screen_state, screen);
+   genX_call(screen->devinfo, init_screen_state, screen);
 
    glsl_type_singleton_init_or_ref();
 
diff --git a/src/gallium/drivers/iris/iris_screen.h b/src/gallium/drivers/iris/iris_screen.h
index eb7322904cf..ce0931c5b7e 100644
--- a/src/gallium/drivers/iris/iris_screen.h
+++ b/src/gallium/drivers/iris/iris_screen.h
@@ -199,7 +199,7 @@ struct iris_screen {
     */
    uint64_t last_seqno;
 
-   struct intel_device_info devinfo;
+   const struct intel_device_info *devinfo;
    struct isl_device isl_dev;
    struct iris_bufmgr *bufmgr;
    struct brw_compiler *compiler;
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 90654b5472d..d188817f98e 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -472,7 +472,7 @@ iris_load_register_reg32(struct iris_batch *batch, uint32_t dst,
                          uint32_t src)
 {
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    mi_store(&b, mi_reg32(dst), mi_reg32(src));
 }
 
@@ -481,7 +481,7 @@ iris_load_register_reg64(struct iris_batch *batch, uint32_t dst,
                          uint32_t src)
 {
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    mi_store(&b, mi_reg64(dst), mi_reg64(src));
 }
 
@@ -490,7 +490,7 @@ iris_load_register_imm32(struct iris_batch *batch, uint32_t reg,
                          uint32_t val)
 {
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    mi_store(&b, mi_reg32(reg), mi_imm(val));
 }
 
@@ -499,7 +499,7 @@ iris_load_register_imm64(struct iris_batch *batch, uint32_t reg,
                          uint64_t val)
 {
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    mi_store(&b, mi_reg64(reg), mi_imm(val));
 }
 
@@ -512,7 +512,7 @@ iris_load_register_mem32(struct iris_batch *batch, uint32_t reg,
 {
    iris_batch_sync_region_start(batch);
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    struct mi_value src = mi_mem32(ro_bo(bo, offset));
    mi_store(&b, mi_reg32(reg), src);
    iris_batch_sync_region_end(batch);
@@ -528,7 +528,7 @@ iris_load_register_mem64(struct iris_batch *batch, uint32_t reg,
 {
    iris_batch_sync_region_start(batch);
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    struct mi_value src = mi_mem64(ro_bo(bo, offset));
    mi_store(&b, mi_reg64(reg), src);
    iris_batch_sync_region_end(batch);
@@ -541,7 +541,7 @@ iris_store_register_mem32(struct iris_batch *batch, uint32_t reg,
 {
    iris_batch_sync_region_start(batch);
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    struct mi_value dst = mi_mem32(rw_bo(bo, offset, IRIS_DOMAIN_OTHER_WRITE));
    struct mi_value src = mi_reg32(reg);
    if (predicated)
@@ -558,7 +558,7 @@ iris_store_register_mem64(struct iris_batch *batch, uint32_t reg,
 {
    iris_batch_sync_region_start(batch);
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    struct mi_value dst = mi_mem64(rw_bo(bo, offset, IRIS_DOMAIN_OTHER_WRITE));
    struct mi_value src = mi_reg64(reg);
    if (predicated)
@@ -575,7 +575,7 @@ iris_store_data_imm32(struct iris_batch *batch,
 {
    iris_batch_sync_region_start(batch);
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    struct mi_value dst = mi_mem32(rw_bo(bo, offset, IRIS_DOMAIN_OTHER_WRITE));
    struct mi_value src = mi_imm(imm);
    mi_store(&b, dst, src);
@@ -589,7 +589,7 @@ iris_store_data_imm64(struct iris_batch *batch,
 {
    iris_batch_sync_region_start(batch);
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    struct mi_value dst = mi_mem64(rw_bo(bo, offset, IRIS_DOMAIN_OTHER_WRITE));
    struct mi_value src = mi_imm(imm);
    mi_store(&b, dst, src);
@@ -802,7 +802,7 @@ iris_enable_obj_preemption(struct iris_batch *batch, bool enable)
 static void
 upload_pixel_hashing_tables(struct iris_batch *batch)
 {
-   UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   UNUSED const struct intel_device_info *devinfo = batch->screen->devinfo;
    UNUSED struct iris_context *ice = batch->ice;
    assert(&ice->batches[IRIS_BATCH_RENDER] == batch);
 
@@ -952,7 +952,7 @@ upload_pixel_hashing_tables(struct iris_batch *batch)
 static void
 iris_alloc_push_constants(struct iris_batch *batch)
 {
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    /* For now, we set a static partitioning of the push constant area,
     * assuming that all stages could be in use.
@@ -1093,7 +1093,7 @@ toggle_protected(struct iris_batch *batch)
 static void
 iris_init_render_context(struct iris_batch *batch)
 {
-   UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   UNUSED const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    iris_batch_sync_region_start(batch);
 
@@ -1228,7 +1228,7 @@ iris_init_render_context(struct iris_batch *batch)
 static void
 iris_init_compute_context(struct iris_batch *batch)
 {
-   UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   UNUSED const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    iris_batch_sync_region_start(batch);
 
@@ -1668,7 +1668,7 @@ static bool
 want_pma_fix(struct iris_context *ice)
 {
    UNUSED struct iris_screen *screen = (void *) ice->ctx.screen;
-   UNUSED const struct intel_device_info *devinfo = &screen->devinfo;
+   UNUSED const struct intel_device_info *devinfo = screen->devinfo;
    const struct brw_wm_prog_data *wm_prog_data = (void *)
       ice->shaders.prog[MESA_SHADER_FRAGMENT]->prog_data;
    const struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
@@ -2190,7 +2190,7 @@ iris_create_sampler_state(struct pipe_context *ctx,
                           const struct pipe_sampler_state *state)
 {
    UNUSED struct iris_screen *screen = (void *)ctx->screen;
-   UNUSED const struct intel_device_info *devinfo = &screen->devinfo;
+   UNUSED const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_sampler_state *cso = CALLOC_STRUCT(iris_sampler_state);
 
    if (!cso)
@@ -2572,7 +2572,7 @@ iris_create_sampler_view(struct pipe_context *ctx,
                          const struct pipe_sampler_view *tmpl)
 {
    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_sampler_view *isv = calloc(1, sizeof(struct iris_sampler_view));
 
    if (!isv)
@@ -2691,7 +2691,7 @@ iris_create_surface(struct pipe_context *ctx,
                     const struct pipe_surface *tmpl)
 {
    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
 
    isl_surf_usage_flags_t usage = 0;
    if (tmpl->writable)
@@ -3013,7 +3013,7 @@ iris_set_sampler_views(struct pipe_context *ctx,
 {
    struct iris_context *ice = (struct iris_context *) ctx;
    UNUSED struct iris_screen *screen = (void *) ctx->screen;
-   UNUSED const struct intel_device_info *devinfo = &screen->devinfo;
+   UNUSED const struct intel_device_info *devinfo = screen->devinfo;
    gl_shader_stage stage = stage_from_pipe(p_stage);
    struct iris_shader_state *shs = &ice->state.shaders[stage];
    unsigned i;
@@ -3290,7 +3290,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
 {
    struct iris_context *ice = (struct iris_context *) ctx;
    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct isl_device *isl_dev = &screen->isl_dev;
    struct pipe_framebuffer_state *cso = &ice->state.framebuffer;
    struct iris_resource *zres;
@@ -3742,7 +3742,7 @@ iris_create_vertex_elements(struct pipe_context *ctx,
                             const struct pipe_vertex_element *state)
 {
    struct iris_screen *screen = (struct iris_screen *)ctx->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_vertex_element_state *cso =
       malloc(sizeof(struct iris_vertex_element_state));
 
@@ -5988,7 +5988,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
          assert(ice->shaders.urb.size[i] != 0);
       }
 
-      intel_get_urb_config(&screen->devinfo,
+      intel_get_urb_config(screen->devinfo,
                            screen->l3_config_3d,
                            ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL,
                            ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL,
@@ -6229,7 +6229,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
 
             uint32_t ps_state[GENX(3DSTATE_PS_length)] = {0};
             _iris_pack_command(batch, GENX(3DSTATE_PS), ps_state, ps) {
-               intel_set_ps_dispatch_state(&ps, &batch->screen->devinfo,
+               intel_set_ps_dispatch_state(&ps, batch->screen->devinfo,
                                            wm_prog_data, cso_fb->samples);
 
                ps.DispatchGRFStartRegisterForConstantSetupData0 =
@@ -6308,7 +6308,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
           * 3dstate_so_buffer_index_0/1/2/3 states to ensure so_buffer_index_* state is
           * not combined with other state changes.
           */
-         if (intel_device_info_is_dg2(&batch->screen->devinfo)) {
+         if (intel_device_info_is_dg2(batch->screen->devinfo)) {
             iris_emit_pipe_control_flush(batch,
                                          "SO pre change stall WA",
                                          PIPE_CONTROL_CS_STALL);
@@ -6345,7 +6345,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
          }
 
          /* Wa_16011411144 */
-         if (intel_device_info_is_dg2(&batch->screen->devinfo)) {
+         if (intel_device_info_is_dg2(batch->screen->devinfo)) {
             iris_emit_pipe_control_flush(batch,
                                          "SO post change stall WA",
                                          PIPE_CONTROL_CS_STALL);
@@ -6359,7 +6359,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
           *    2. Send SO_DECL NP state
           *    3. Send 3D State SOL with SOL Enabled
           */
-         if (intel_device_info_is_dg2(&batch->screen->devinfo))
+         if (intel_device_info_is_dg2(batch->screen->devinfo))
             iris_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol);
 
          uint32_t *decl_list =
@@ -6883,7 +6883,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
                                                                RR_FREE;
          vfg.DistributionGranularity = BatchLevelGranularity;
          /* Wa_14014890652 */
-         if (intel_device_info_is_dg2(&batch->screen->devinfo))
+         if (intel_device_info_is_dg2(batch->screen->devinfo))
             vfg.GranularityThresholdDisable = 1;
          vfg.ListCutIndexEnable = draw->primitive_restart;
          /* 192 vertices for TRILIST_ADJ */
@@ -7066,7 +7066,7 @@ iris_upload_render_state(struct iris_context *ice,
 #define _3DPRIM_BASE_VERTEX         0x2440
 
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
 
    if (indirect && !indirect->count_from_stream_output) {
       if (indirect->indirect_draw_count) {
@@ -7206,7 +7206,7 @@ iris_load_indirect_location(struct iris_context *ice,
    struct iris_state_ref *grid_size = &ice->state.grid_size;
    struct iris_bo *bo = iris_resource_bo(grid_size->res);
    struct mi_builder b;
-   mi_builder_init(&b, &batch->screen->devinfo, batch);
+   mi_builder_init(&b, batch->screen->devinfo, batch);
    struct mi_value size_x = mi_mem32(ro_bo(bo, grid_size->offset + 0));
    struct mi_value size_y = mi_mem32(ro_bo(bo, grid_size->offset + 4));
    struct mi_value size_z = mi_mem32(ro_bo(bo, grid_size->offset + 8));
@@ -7224,7 +7224,7 @@ iris_upload_compute_walker(struct iris_context *ice,
 {
    const uint64_t stage_dirty = ice->state.stage_dirty;
    struct iris_screen *screen = batch->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_binder *binder = &ice->state.binder;
    struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_COMPUTE];
    struct iris_compiled_shader *shader =
@@ -7292,7 +7292,7 @@ iris_upload_gpgpu_walker(struct iris_context *ice,
 {
    const uint64_t stage_dirty = ice->state.stage_dirty;
    struct iris_screen *screen = batch->screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct intel_device_info *devinfo = screen->devinfo;
    struct iris_binder *binder = &ice->state.binder;
    struct iris_shader_state *shs = &ice->state.shaders[MESA_SHADER_COMPUTE];
    struct iris_uncompiled_shader *ish =
@@ -7717,7 +7717,7 @@ iris_rebind_buffer(struct iris_context *ice,
 static void
 batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
 {
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
 
    iris_batch_sync_boundary(batch);
 
@@ -7863,7 +7863,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
                            uint32_t offset,
                            uint64_t imm)
 {
-   UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   UNUSED const struct intel_device_info *devinfo = batch->screen->devinfo;
    enum pipe_control_flags post_sync_flags = get_post_sync_flags(flags);
    enum pipe_control_flags non_lri_post_sync_flags =
       post_sync_flags & ~PIPE_CONTROL_LRI_POST_SYNC_OP;
@@ -8430,7 +8430,7 @@ genX(emit_hashing_mode)(struct iris_context *ice, struct iris_batch *batch,
                         unsigned width, unsigned height, unsigned scale)
 {
 #if GFX_VER == 9
-   const struct intel_device_info *devinfo = &batch->screen->devinfo;
+   const struct intel_device_info *devinfo = batch->screen->devinfo;
    const unsigned slice_hashing[] = {
       /* Because all Gfx9 platforms with more than one slice require
        * three-way subslice hashing, a single "normal" 16x16 slice hashing
@@ -8516,7 +8516,7 @@ iris_set_frontend_noop(struct pipe_context *ctx, bool enable)
 void
 genX(init_screen_state)(struct iris_screen *screen)
 {
-   assert(screen->devinfo.verx10 == GFX_VERx10);
+   assert(screen->devinfo->verx10 == GFX_VERx10);
    screen->vtbl.destroy_state = iris_destroy_state;
    screen->vtbl.init_render_context = iris_init_render_context;
    screen->vtbl.init_compute_context = iris_init_compute_context;
diff --git a/src/gallium/drivers/iris/iris_utrace.c b/src/gallium/drivers/iris/iris_utrace.c
index 7f49826d707..16ac6eea589 100644
--- a/src/gallium/drivers/iris/iris_utrace.c
+++ b/src/gallium/drivers/iris/iris_utrace.c
@@ -82,7 +82,7 @@ iris_utrace_read_ts(struct u_trace_context *utctx,
    if (ts[idx] == U_TRACE_NO_TIMESTAMP)
       return U_TRACE_NO_TIMESTAMP;
 
-   return intel_device_info_timebase_scale(&screen->devinfo, ts[idx]);
+   return intel_device_info_timebase_scale(screen->devinfo, ts[idx]);
 }
 
 static void
@@ -114,7 +114,7 @@ void iris_utrace_init(struct iris_context *ice)
    /* We could be dealing with /dev/dri/card0 or /dev/dri/renderD128 so to get
     * a GPU ID we % 128 the minor number.
     */
-   intel_ds_device_init(&ice->ds, &screen->devinfo, screen->fd, minor % 128,
+   intel_ds_device_init(&ice->ds, screen->devinfo, screen->fd, minor % 128,
                         INTEL_DS_API_OPENGL);
    u_trace_pipe_context_init(&ice->ds.trace_context, &ice->ctx,
                              iris_utrace_record_ts,