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r200: align for mipmap tree changes

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This commit is contained in:
Maciej Cencora 2009-11-17 19:46:59 +01:00
parent 93eb2ab8c3
commit afe84fa698
3 changed files with 14 additions and 30 deletions
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2
src/mesa/drivers/dri/r200/r200_state_init.c
View file

@ -640,7 +640,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
OUT_BATCH_TABLE(atom->cmd, 10);
if (t && t->mt && !t->image_override) {
OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, get_base_teximage_offset(t),
RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
} else if (!t) {
/* workaround for old CS mechanism */

21
src/mesa/drivers/dri/r200/r200_tex.c
View file

@ -385,16 +385,7 @@ static void r200TexParameter( GLcontext *ctx, GLenum target,
case GL_TEXTURE_MAX_LEVEL:
case GL_TEXTURE_MIN_LOD:
case GL_TEXTURE_MAX_LOD:
/* This isn't the most efficient solution but there doesn't appear to
* be a nice alternative. Since there's no LOD clamping,
* we just have to rely on loading the right subset of mipmap levels
* to simulate a clamped LOD.
*/
if (t->mt) {
radeon_miptree_unreference(t->mt);
t->mt = 0;
t->validated = GL_FALSE;
}
t->validated = GL_FALSE;
break;
default:
@ -413,7 +404,7 @@ static void r200DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
(void *)texObj,
_mesa_lookup_enum_by_nr(texObj->Target));
}
if (rmesa) {
int i;
radeon_firevertices(&rmesa->radeon);
@ -425,11 +416,9 @@ static void r200DeleteTexture(GLcontext * ctx, struct gl_texture_object *texObj)
}
}
}
if (t->mt) {
radeon_miptree_unreference(t->mt);
t->mt = 0;
}
radeon_miptree_unreference(&t->mt);
_mesa_delete_texture_object(ctx, texObj);
}

21
src/mesa/drivers/dri/r200/r200_texstate.c
View file

@ -824,14 +824,10 @@ void r200SetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint glx_texture_fo
radeon_bo_unref(rImage->bo);
rImage->bo = NULL;
}
if (t->mt) {
radeon_miptree_unreference(t->mt);
t->mt = NULL;
}
if (rImage->mt) {
radeon_miptree_unreference(rImage->mt);
rImage->mt = NULL;
}
radeon_miptree_unreference(&t->mt);
radeon_miptree_unreference(&rImage->mt);
_mesa_init_teximage_fields(radeon->glCtx, target, texImage,
rb->base.Width, rb->base.Height, 1, 0, rb->cpp);
texImage->RowStride = rb->pitch / rb->cpp;
@ -1423,10 +1419,9 @@ void set_re_cntl_d3d( GLcontext *ctx, int unit, GLboolean use_d3d )
*/
static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t)
{
int firstlevel = t->mt ? t->mt->firstLevel : 0;
const struct gl_texture_image *firstImage = t->base.Image[0][firstlevel];
const struct gl_texture_image *firstImage = t->base.Image[0][t->minLod];
GLint log2Width, log2Height, log2Depth, texelBytes;
if ( t->bo ) {
return;
}
@ -1454,9 +1449,9 @@ static void setup_hardware_state(r200ContextPtr rmesa, radeonTexObj *t)
return;
}
}
t->pp_txfilter &= ~R200_MAX_MIP_LEVEL_MASK;
t->pp_txfilter |= (t->mt->lastLevel - t->mt->firstLevel) << R200_MAX_MIP_LEVEL_SHIFT;
t->pp_txfilter |= (t->maxLod - t->minLod) << R200_MAX_MIP_LEVEL_SHIFT;
t->pp_txformat &= ~(R200_TXFORMAT_WIDTH_MASK |
R200_TXFORMAT_HEIGHT_MASK |