diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index bcd75c2f28a..db0d6e0f7be 100644
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -190,6 +190,10 @@ v3d_qpu_add_op_name(enum v3d_qpu_add_op op)
                 [V3D_QPU_A_ROTQ] = "rotq",
                 [V3D_QPU_A_ROT] = "rot",
                 [V3D_QPU_A_SHUFFLE] = "shuffle",
+                [V3D_QPU_A_SETNNMODE_UU] = "setnnmode_uu",
+                [V3D_QPU_A_SETNNMODE_SU] = "setnnmode_su",
+                [V3D_QPU_A_SETNNMODE_US] = "setnnmode_us",
+                [V3D_QPU_A_SETNNMODE_SS] = "setnnmode_ss",
         };
 
         if (op >= ARRAY_SIZE(op_names))
@@ -223,6 +227,7 @@ v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op)
                 [V3D_QPU_M_FUNPACKSNORMHI] = "funpacksnormhi",
                 [V3D_QPU_M_VFTOUNORM10LO] = "vftounorm10lo",
                 [V3D_QPU_M_VFTOUNORM10HI] = "vftounorm10hi",
+                [V3D_QPU_M_V8DOT] = "v8dot",
         };
 
         if (op >= ARRAY_SIZE(op_names))
@@ -503,6 +508,10 @@ static const uint8_t add_op_args[] = {
         [V3D_QPU_A_ROTQ] = D | A | B,
         [V3D_QPU_A_ROT] = D | A | B,
         [V3D_QPU_A_SHUFFLE] = D | A | B,
+        [V3D_QPU_A_SETNNMODE_UU] = 0,
+        [V3D_QPU_A_SETNNMODE_SU] = 0,
+        [V3D_QPU_A_SETNNMODE_US] = 0,
+        [V3D_QPU_A_SETNNMODE_SS] = 0,
 };
 
 static const uint8_t mul_op_args[] = {
@@ -527,6 +536,7 @@ static const uint8_t mul_op_args[] = {
         [V3D_QPU_M_FUNPACKSNORMHI] = D | A,
         [V3D_QPU_M_VFTOUNORM10LO] = D | A,
         [V3D_QPU_M_VFTOUNORM10HI] = D | A,
+        [V3D_QPU_M_V8DOT] = D | A | B,
 };
 
 bool
diff --git a/src/broadcom/qpu/qpu_instr.h b/src/broadcom/qpu/qpu_instr.h
index a353fd9c986..9097f0effa2 100644
--- a/src/broadcom/qpu/qpu_instr.h
+++ b/src/broadcom/qpu/qpu_instr.h
@@ -242,6 +242,10 @@ enum v3d_qpu_add_op {
         V3D_QPU_A_ROTQ,
         V3D_QPU_A_ROT,
         V3D_QPU_A_SHUFFLE,
+        V3D_QPU_A_SETNNMODE_UU,
+        V3D_QPU_A_SETNNMODE_SU,
+        V3D_QPU_A_SETNNMODE_US,
+        V3D_QPU_A_SETNNMODE_SS,
 };
 
 enum v3d_qpu_mul_op {
@@ -275,6 +279,7 @@ enum v3d_qpu_mul_op {
         V3D_QPU_M_FUNPACKSNORMHI,
         V3D_QPU_M_VFTOUNORM10LO,
         V3D_QPU_M_VFTOUNORM10HI,
+        V3D_QPU_M_V8DOT,
 };
 
 enum v3d_qpu_output_pack {
diff --git a/src/broadcom/qpu/qpu_pack.c b/src/broadcom/qpu/qpu_pack.c
index 291dcc74627..c82ac492d6d 100644
--- a/src/broadcom/qpu/qpu_pack.c
+++ b/src/broadcom/qpu/qpu_pack.c
@@ -644,6 +644,11 @@ static const struct opcode_desc v3d71_add_ops[] = {
         { 187, 187, .raddr_mask = OP_RANGE(32, 34), V3D_QPU_A_FXCD },
         { 187, 187, .raddr_mask = OP_RANGE(36, 38), V3D_QPU_A_FYCD },
 
+        { 187, 187, .raddr_mask = OP_MASK(48), V3D_QPU_A_SETNNMODE_UU, 71 },
+        { 187, 187, .raddr_mask = OP_MASK(49), V3D_QPU_A_SETNNMODE_SU, 71 },
+        { 187, 187, .raddr_mask = OP_MASK(50), V3D_QPU_A_SETNNMODE_US, 71 },
+        { 187, 187, .raddr_mask = OP_MASK(51), V3D_QPU_A_SETNNMODE_SS, 71 },
+
         { 188, 188, .raddr_mask = OP_MASK(0), V3D_QPU_A_LDVPMV_IN, 71 },
         { 188, 188, .raddr_mask = OP_MASK(1), V3D_QPU_A_LDVPMD_IN, 71 },
         { 188, 188, .raddr_mask = OP_MASK(2), V3D_QPU_A_LDVPMP, 71 },
@@ -755,6 +760,8 @@ static const struct opcode_desc v3d71_mul_ops[] = {
         { 9, 9, .raddr_mask = ANYOPMASK, V3D_QPU_M_SMUL24, 71 },
         { 10, 10, .raddr_mask = ANYOPMASK, V3D_QPU_M_MULTOP, 71 },
 
+        { 11, 11, .raddr_mask = ANYOPMASK, V3D_QPU_M_V8DOT, 71 },
+
         { 14, 14, .raddr_mask = OP_RANGE(0, 2),   V3D_QPU_M_FMOV, 71 },
         { 14, 14, .raddr_mask = OP_RANGE(4, 6),   V3D_QPU_M_FMOV, 71 },
         { 14, 14, .raddr_mask = OP_RANGE(8, 10),  V3D_QPU_M_FMOV, 71 },