From af35a99435c3a47ce634c427392436ae815a74fb Mon Sep 17 00:00:00 2001 From: Trigger Huang Date: Fri, 6 Feb 2026 12:18:00 +0800 Subject: [PATCH] radv: supports protected memory allocation Add memory type for protected memory to support TMZ encrypted memory allocation Signed-off-by: Trigger Huang Part-of: --- src/amd/vulkan/radv_physical_device.c | 52 +++++++++++++++++++ src/amd/vulkan/radv_radeon_winsys.h | 1 + src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 7 +++ 3 files changed, 60 insertions(+) diff --git a/src/amd/vulkan/radv_physical_device.c b/src/amd/vulkan/radv_physical_device.c index 07fe0a5ed58..e57a156fb1f 100644 --- a/src/amd/vulkan/radv_physical_device.c +++ b/src/amd/vulkan/radv_physical_device.c @@ -571,6 +571,58 @@ radv_physical_device_init_mem_types(struct radv_physical_device *pdev) } pdev->memory_properties.memoryTypeCount = type_count; + if (radv_tmz_enabled(pdev)) { + if (vram_index >= 0 || visible_vram_index >= 0) { + pdev->memory_domains[type_count] = RADEON_DOMAIN_VRAM; + pdev->memory_flags[type_count] = RADEON_FLAG_ENCRYPTED | RADEON_FLAG_NO_CPU_ACCESS; + pdev->memory_properties.memoryTypes[type_count++] = (VkMemoryType){ + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | VK_MEMORY_PROPERTY_PROTECTED_BIT, + .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index, + }; + + pdev->memory_domains[type_count] = RADEON_DOMAIN_VRAM; + pdev->memory_flags[type_count] = RADEON_FLAG_ENCRYPTED | RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_32BIT; + pdev->memory_properties.memoryTypes[type_count++] = (VkMemoryType){ + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | VK_MEMORY_PROPERTY_PROTECTED_BIT, + .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index, + }; + } + + if (visible_vram_index >= 0) { + pdev->memory_domains[type_count] = RADEON_DOMAIN_VRAM; + pdev->memory_flags[type_count] = RADEON_FLAG_ENCRYPTED; + pdev->memory_properties.memoryTypes[type_count++] = (VkMemoryType){ + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | VK_MEMORY_PROPERTY_PROTECTED_BIT, + .heapIndex = visible_vram_index, + }; + + pdev->memory_domains[type_count] = RADEON_DOMAIN_VRAM; + pdev->memory_flags[type_count] = RADEON_FLAG_ENCRYPTED | RADEON_FLAG_32BIT; + pdev->memory_properties.memoryTypes[type_count++] = (VkMemoryType){ + .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT | VK_MEMORY_PROPERTY_PROTECTED_BIT, + .heapIndex = visible_vram_index, + }; + } + + if (gart_index >= 0) { + pdev->memory_domains[type_count] = RADEON_DOMAIN_GTT; + pdev->memory_flags[type_count] = RADEON_FLAG_ENCRYPTED; + pdev->memory_properties.memoryTypes[type_count++] = (VkMemoryType){ + .propertyFlags = VK_MEMORY_PROPERTY_PROTECTED_BIT, + .heapIndex = gart_index, + }; + + pdev->memory_domains[type_count] = RADEON_DOMAIN_GTT; + pdev->memory_flags[type_count] = RADEON_FLAG_ENCRYPTED | RADEON_FLAG_32BIT; + pdev->memory_properties.memoryTypes[type_count++] = (VkMemoryType){ + .propertyFlags = VK_MEMORY_PROPERTY_PROTECTED_BIT, + .heapIndex = gart_index, + }; + } + + pdev->memory_properties.memoryTypeCount = type_count; + } + if (pdev->info.has_l2_uncached) { for (int i = 0; i < pdev->memory_properties.memoryTypeCount; i++) { VkMemoryType mem_type = pdev->memory_properties.memoryTypes[i]; diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index a393de18391..2544a8c1f05 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -52,6 +52,7 @@ enum radeon_bo_flag { /* bitfield */ RADEON_FLAG_GFX12_ALLOW_DCC = (1 << 13), RADEON_FLAG_VM_UPDATE_WAIT = (1 << 14), RADEON_FLAG_VM_PAD_1PAGE = (1 << 15), + RADEON_FLAG_ENCRYPTED = (1 << 16), }; enum radeon_ctx_priority { diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c index 09d4cab6adc..918e9d4eb40 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c @@ -509,6 +509,11 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws, uint64_t size, unsigned request.flags |= AMDGPU_GEM_CREATE_GFX12_DCC; } + if (flags & RADEON_FLAG_ENCRYPTED) { + assert(ws->info.has_tmz_support); + request.flags |= AMDGPU_GEM_CREATE_ENCRYPTED; + } + r = ac_drm_bo_alloc(ws->dev, &request, &buf_handle); if (r) { fprintf(stderr, "radv/amdgpu: Failed to allocate a buffer:\n"); @@ -913,6 +918,8 @@ radv_amdgpu_bo_get_flags_from_fd(struct radeon_winsys *_ws, int fd, enum radeon_ *flags |= RADEON_FLAG_DISCARDABLE; if (info.alloc_flags & AMDGPU_GEM_CREATE_GFX12_DCC) *flags |= RADEON_FLAG_GFX12_ALLOW_DCC; + if (info.alloc_flags & AMDGPU_GEM_CREATE_ENCRYPTED) + *flags |= RADEON_FLAG_ENCRYPTED; return true; }