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anv: Use a separate field in the pipeline for compute shader

Browse source 
This is a preparation for splitting the compute and graphics pipelines
into separate structs.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4040>
This commit is contained in:
Caio Marcelo de Oliveira Filho 2020-03-03 13:43:39 -08:00
parent bff45b6a7f
commit af33f0d767
5 changed files with 42 additions and 20 deletions
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8
src/intel/vulkan/anv_cmd_buffer.c
View file

@ -426,9 +426,8 @@ void anv_CmdBindPipeline(
cmd_buffer->state.compute.base.pipeline = pipeline;
cmd_buffer->state.compute.pipeline_dirty = true;
const struct anv_pipeline_bind_map *bind_map =
&pipeline->shaders[MESA_SHADER_COMPUTE]->bind_map;
set_dirty_for_bind_map(cmd_buffer, MESA_SHADER_COMPUTE, bind_map);
set_dirty_for_bind_map(cmd_buffer, MESA_SHADER_COMPUTE,
&pipeline->cs->bind_map);
break;
}
@ -822,8 +821,7 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
&cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct anv_push_range *range =
&pipeline->shaders[MESA_SHADER_COMPUTE]->bind_map.push_ranges[0];
const struct anv_push_range *range = &pipeline->cs->bind_map.push_ranges[0];
if (cs_prog_data->push.total.size == 0)
return (struct anv_state) { .offset = 0 };

34
src/intel/vulkan/anv_pipeline.c
View file

@ -301,9 +301,21 @@ void anv_DestroyPipeline(
if (pipeline->blend_state.map)
anv_state_pool_free(&device->dynamic_state_pool, pipeline->blend_state);
for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
if (pipeline->shaders[s])
anv_shader_bin_unref(device, pipeline->shaders[s]);
switch (pipeline->type) {
case ANV_PIPELINE_GRAPHICS:
for (unsigned s = 0; s < MESA_SHADER_STAGES; s++) {
if (pipeline->shaders[s])
anv_shader_bin_unref(device, pipeline->shaders[s]);
}
break;
case ANV_PIPELINE_COMPUTE:
if (pipeline->cs)
anv_shader_bin_unref(device, pipeline->cs);
break;
default:
unreachable("invalid pipeline type");
}
vk_free2(&device->alloc, pAllocator, pipeline);
@ -1586,7 +1598,7 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
}
pipeline->active_stages = VK_SHADER_STAGE_COMPUTE_BIT;
pipeline->shaders[MESA_SHADER_COMPUTE] = bin;
pipeline->cs = bin;
return VK_SUCCESS;
}
@ -2028,8 +2040,18 @@ VkResult anv_GetPipelineExecutableStatisticsKHR(
const struct anv_pipeline_executable *exe =
anv_pipeline_get_executable(pipeline, pExecutableInfo->executableIndex);
const struct brw_stage_prog_data *prog_data =
pipeline->shaders[exe->stage]->prog_data;
const struct brw_stage_prog_data *prog_data;
switch (pipeline->type) {
case ANV_PIPELINE_GRAPHICS:
prog_data = pipeline->shaders[exe->stage]->prog_data;
break;
case ANV_PIPELINE_COMPUTE:
prog_data = pipeline->cs->prog_data;
break;
default:
unreachable("invalid pipeline type");
}
vk_outarray_append(&out, stat) {
WRITE_STR(stat->name, "Instruction Count");

9
src/intel/vulkan/anv_private.h
View file

@ -3179,6 +3179,7 @@ struct anv_pipeline {
struct anv_subpass * subpass;
struct anv_shader_bin * shaders[MESA_SHADER_STAGES];
struct anv_shader_bin * cs;
struct util_dynarray executables;
@ -3251,7 +3252,13 @@ ANV_DECL_GET_PROG_DATA_FUNC(tcs, MESA_SHADER_TESS_CTRL)
ANV_DECL_GET_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
ANV_DECL_GET_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
ANV_DECL_GET_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
ANV_DECL_GET_PROG_DATA_FUNC(cs, MESA_SHADER_COMPUTE)
static inline const struct brw_cs_prog_data *
get_cs_prog_data(const struct anv_pipeline *pipeline)
{
assert(pipeline->type == ANV_PIPELINE_COMPUTE);
return (const struct brw_cs_prog_data *) pipeline->cs->prog_data;
}
static inline const struct brw_vue_prog_data *
anv_pipeline_get_last_vue_prog_data(const struct anv_pipeline *pipeline)

2
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -4150,7 +4150,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->state.compute.pipeline_dirty) {
flush_descriptor_sets(cmd_buffer,
&cmd_buffer->state.compute.base,
&pipeline->shaders[MESA_SHADER_COMPUTE], 1);
&pipeline->cs, 1);
uint32_t iface_desc_data_dw[GENX(INTERFACE_DESCRIPTOR_DATA_length)];
struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {

9
src/intel/vulkan/genX_pipeline.c
View file

@ -2251,11 +2251,7 @@ compute_pipeline_create(
pipeline->mem_ctx = ralloc_context(NULL);
pipeline->flags = pCreateInfo->flags;
/* When we free the pipeline, we detect stages based on the NULL status
* of various prog_data pointers. Make them NULL by default.
*/
memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
pipeline->cs = NULL;
util_dynarray_init(&pipeline->executables, pipeline->mem_ctx);
@ -2290,8 +2286,7 @@ compute_pipeline_create(
const uint32_t subslices = MAX2(device->physical->subslice_total, 1);
const struct anv_shader_bin *cs_bin =
pipeline->shaders[MESA_SHADER_COMPUTE];
const struct anv_shader_bin *cs_bin = pipeline->cs;
anv_batch_emit(&pipeline->batch, GENX(MEDIA_VFE_STATE), vfe) {
#if GEN_GEN > 7