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cell: initial support for IF/ELSE/ENDIF in fragment shader codegen
Only one level of if/else/endif nesting is currently working.
This commit is contained in:
Brian Paul
parent
5ab221549d
commit
af2ca5dc38
1 changed files with 177 additions and 20 deletions
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@ -71,6 +71,11 @@ struct codegen
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int num_itemps;
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int itemps[3];
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/** Current IF/ELSE/ENDIF nesting level */
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int if_nesting;
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/** Index of execution mask register */
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int exec_mask_reg;
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struct spe_function *f;
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boolean error;
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};
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@ -112,18 +117,43 @@ get_const_one_reg(struct codegen *gen)
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{
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if (gen->one_reg <= 0) {
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gen->one_reg = spe_allocate_available_register(gen->f);
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/* one = {1.0, 1.0, 1.0, 1.0} */
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spe_load_float(gen->f, gen->one_reg, 1.0f);
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#if DISASSEM
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printf("\til\tr%d, 1.0f\n", gen->one_reg);
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#endif
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}
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/* one = {1.0, 1.0, 1.0, 1.0} */
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spe_load_float(gen->f, gen->one_reg, 1.0f);
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#if DISASSEM
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printf("il\tr%d, 1.0f\n", gen->one_reg);
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#endif
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return gen->one_reg;
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}
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/**
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* Return index of the pixel execution mask.
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* The register is allocated an initialized upon the first call.
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*
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* The pixel execution mask controls which pixels in a quad are
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* modified, according to surrounding conditionals, loops, etc.
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*/
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static int
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get_exec_mask_reg(struct codegen *gen)
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{
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if (gen->exec_mask_reg <= 0) {
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gen->exec_mask_reg = spe_allocate_available_register(gen->f);
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/* exec_mask = {~0, ~0, ~0, ~0} */
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spe_load_int(gen->f, gen->exec_mask_reg, ~0);
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#if DISASSEM
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printf("INIT EXEC MASK:\n");
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printf("\tload\tr%d, 0x%x\n", gen->exec_mask_reg, ~0);
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#endif
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}
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return gen->exec_mask_reg;
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}
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/**
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* Return the index of the SPU temporary containing the named TGSI
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* source register. If the TGSI register is a TGSI_FILE_TEMPORARY we
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@ -136,7 +166,7 @@ get_src_reg(struct codegen *gen,
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int channel,
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const struct tgsi_full_src_register *src)
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{
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int reg;
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int reg = -1;
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int swizzle = tgsi_util_get_full_src_register_extswizzle(src, channel);
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assert(swizzle >= 0);
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@ -156,7 +186,7 @@ get_src_reg(struct codegen *gen,
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/* Load: reg = memory[(machine_reg) + offset] */
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spe_lqd(gen->f, reg, gen->inputs_reg, offset);
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#if DISASSEM
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printf("lqd\tr%d, r%d + %d\n", reg, gen->inputs_reg, offset);
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printf("\tlqd\tr%d, r%d + %d\n", reg, gen->inputs_reg, offset);
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#endif
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}
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break;
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@ -184,11 +214,14 @@ get_dst_reg(struct codegen *gen,
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int channel,
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const struct tgsi_full_dst_register *dest)
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{
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int reg;
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int reg = -1;
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switch (dest->DstRegister.File) {
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case TGSI_FILE_TEMPORARY:
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reg = gen->temp_regs[dest->DstRegister.Index][channel];
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if (gen->if_nesting > 0)
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reg = get_itemp(gen);
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else
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reg = gen->temp_regs[dest->DstRegister.Index][channel];
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break;
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case TGSI_FILE_OUTPUT:
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reg = get_itemp(gen);
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@ -214,17 +247,56 @@ store_dest_reg(struct codegen *gen,
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{
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switch (dest->DstRegister.File) {
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case TGSI_FILE_TEMPORARY:
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/* no-op */
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if (gen->if_nesting > 0) {
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int d_reg = gen->temp_regs[dest->DstRegister.Index][channel];
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int exec_reg = get_exec_mask_reg(gen);
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/* Mix d with new value according to exec mask:
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* d[i] = mask_reg[i] ? value_reg : d_reg
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*/
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spe_selb(gen->f, d_reg, d_reg, value_reg, exec_reg);
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#if DISASSEM
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printf("\tselb\tr%d, r%d, r%d, r%d # EXEC MASK'ed\n",
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d_reg, d_reg, value_reg, exec_reg);
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#endif
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}
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else {
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/* we're not inside a condition or loop: do nothing special */
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}
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break;
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case TGSI_FILE_OUTPUT:
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{
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/* offset is measured in quadwords, not bytes */
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int offset = dest->DstRegister.Index * 4 + channel;
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/* Store: memory[(machine_reg) + offset] = reg */
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spe_stqd(gen->f, value_reg, gen->outputs_reg, offset);
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if (gen->if_nesting > 0) {
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int exec_reg = get_exec_mask_reg(gen);
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int curval_reg = get_itemp(gen);
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/* First read the current value from memory:
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* Load: curval = memory[(machine_reg) + offset]
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*/
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spe_lqd(gen->f, curval_reg, gen->outputs_reg, offset);
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/* Mix curval with newvalue according to exec mask:
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* d[i] = mask_reg[i] ? value_reg : d_reg
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*/
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spe_selb(gen->f, curval_reg, curval_reg, value_reg, exec_reg);
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/* Store: memory[(machine_reg) + offset] = curval */
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spe_stqd(gen->f, curval_reg, gen->outputs_reg, offset);
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#if DISASSEM
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printf("stqd\tr%d, r%d + %d\n", value_reg, gen->outputs_reg, offset);
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printf("\tlqd\tr%d, r%d + %d\n",
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curval_reg, gen->outputs_reg, offset);
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printf("\tselb\tr%d, r%d, r%d, r%d # EXEC MASK'ed\n",
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curval_reg, curval_reg, value_reg, exec_reg);
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printf("\tstqd\tr%d, r%d + %d\n",
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curval_reg, gen->outputs_reg, offset);
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#endif
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}
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else {
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/* Store: memory[(machine_reg) + offset] = reg */
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spe_stqd(gen->f, value_reg, gen->outputs_reg, offset);
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#if DISASSEM
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printf("\tstqd\tr%d, r%d + %d\n",
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value_reg, gen->outputs_reg, offset);
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#endif
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}
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}
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break;
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default:
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@ -237,6 +309,9 @@ static boolean
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emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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#if DISASSEM
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printf("MOV:\n");
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#endif
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int src_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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@ -244,7 +319,7 @@ emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
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/* XXX we don't always need to actually emit a mov instruction here */
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spe_move(gen->f, dst_reg, src_reg);
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#if DISASSEM
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printf("mov\tr%d, r%d\n", dst_reg, src_reg);
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printf("\tmov\tr%d, r%d\n", dst_reg, src_reg);
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#endif
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store_dest_reg(gen, dst_reg, ch, &inst->FullDstRegisters[0]);
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free_itemps(gen);
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@ -254,6 +329,7 @@ emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
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}
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/**
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* Emit addition instructions. Recall that a single TGSI_OPCODE_ADD
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* becomes (up to) four SPU "fa" instructions because we're doing SOA
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@ -263,6 +339,9 @@ static boolean
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emit_ADD(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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#if DISASSEM
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printf("ADD:\n");
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#endif
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/* Loop over Red/Green/Blue/Alpha channels */
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for (ch = 0; ch < 4; ch++) {
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/* If the dest R, G, B or A writemask is enabled... */
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@ -275,7 +354,7 @@ emit_ADD(struct codegen *gen, const struct tgsi_full_instruction *inst)
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/* Emit actual SPE instruction: d = s1 + s2 */
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spe_fa(gen->f, d_reg, s1_reg, s2_reg);
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#if DISASSEM
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printf("fa\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
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printf("\tfa\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
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#endif
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/* Store the result (a no-op for TGSI_FILE_TEMPORARY dests) */
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@ -295,6 +374,9 @@ static boolean
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emit_MUL(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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#if DISASSEM
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printf("MUL:\n");
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#endif
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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@ -303,7 +385,7 @@ emit_MUL(struct codegen *gen, const struct tgsi_full_instruction *inst)
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/* d = s1 * s2 */
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spe_fm(gen->f, d_reg, s1_reg, s2_reg);
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#if DISASSEM
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printf("fm\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
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printf("\tfm\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
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#endif
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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free_itemps(gen);
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@ -324,6 +406,9 @@ emit_SGT(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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#if DISASSEM
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printf("SGT:\n");
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#endif
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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@ -333,14 +418,14 @@ emit_SGT(struct codegen *gen, const struct tgsi_full_instruction *inst)
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/* d = (s1 > s2) */
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spe_fcgt(gen->f, d_reg, s1_reg, s2_reg);
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#if DISASSEM
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printf("fcgt\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
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printf("\tfcgt\tr%d, r%d, r%d\n", d_reg, s1_reg, s2_reg);
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#endif
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/* convert d from 0x0/0xffffffff to 0.0/1.0 */
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/* d = d & one_reg */
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spe_and(gen->f, d_reg, d_reg, get_const_one_reg(gen));
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#if DISASSEM
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printf("and\tr%d, r%d, r%d\n", d_reg, d_reg, get_const_one_reg(gen));
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printf("\tand\tr%d, r%d, r%d\n", d_reg, d_reg, get_const_one_reg(gen));
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#endif
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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@ -352,6 +437,71 @@ emit_SGT(struct codegen *gen, const struct tgsi_full_instruction *inst)
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}
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static boolean
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emit_IF(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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const int channel = 0;
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const int exec_reg = get_exec_mask_reg(gen);
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/* update execution mask with the predicate register */
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int tmp_reg = spe_allocate_available_register(gen->f);
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int s1_reg = get_src_reg(gen, channel, &inst->FullSrcRegisters[0]);
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/* tmp = (s1_reg == 0) */
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spe_ceqi(gen->f, tmp_reg, s1_reg, 0);
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/* tmp = !tmp */
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spe_complement(gen->f, tmp_reg);
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/* exec_mask = exec_mask & tmp */
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spe_and(gen->f, exec_reg, exec_reg, tmp_reg);
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#if DISASSEM
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printf("IF:\n");
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printf("\tseqi\tr%d, r%d, 0;\n", tmp_reg, s1_reg);
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printf("\tcomp\tr%d\n", tmp_reg);
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printf("\tand\tr%d, r%d, r%d\n", exec_reg, exec_reg, tmp_reg);
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#endif
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gen->if_nesting++;
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spe_release_register(gen->f, tmp_reg);
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return true;
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}
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static boolean
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emit_ELSE(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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const int exec_reg = get_exec_mask_reg(gen);
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/* exec_mask = !exec_mask */
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spe_complement(gen->f, exec_reg);
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#if DISASSEM
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printf("ELSE:\n");
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printf("\tcomp\tr%d;\n", exec_reg);
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#endif
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return true;
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}
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static boolean
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emit_ENDIF(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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const int exec_reg = get_exec_mask_reg(gen);
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/* XXX todo: pop execution mask */
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spe_load_int(gen->f, exec_reg, ~0x0);
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#if DISASSEM
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printf("ENDIF:\n");
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printf("\tli\tr%d, ~0x0\n", exec_reg);
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#endif
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gen->if_nesting--;
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return true;
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}
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/**
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* Emit END instruction.
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* We just return from the shader function at this point.
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@ -365,7 +515,7 @@ emit_END(struct codegen *gen)
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/* return from function call */
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spe_bi(gen->f, SPE_REG_RA, 0, 0);
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#if DISASSEM
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printf("bi\trRA\n");
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printf("\tbi\trRA\n");
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#endif
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return true;
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}
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@ -390,6 +540,13 @@ emit_instruction(struct codegen *gen,
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case TGSI_OPCODE_END:
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return emit_END(gen);
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case TGSI_OPCODE_IF:
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return emit_IF(gen, inst);
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case TGSI_OPCODE_ELSE:
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return emit_ELSE(gen, inst);
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case TGSI_OPCODE_ENDIF:
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return emit_ENDIF(gen, inst);
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/* XXX lots more cases to do... */
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default:
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