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radv/llvm: Remove dead code.

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Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28430>
This commit is contained in:
Timur Kristóf 2024-03-27 16:09:39 +01:00 • committed by Marge Bot
parent 3a10d1be0e
commit af2a0ea452
1 changed files with 0 additions and 66 deletions
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66
src/amd/vulkan/radv_nir_to_llvm.c
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@ -53,12 +53,6 @@ struct radv_shader_context {
unsigned max_workgroup_size; unsigned max_workgroup_size;
LLVMContextRef context; LLVMContextRef context;
struct ac_llvm_pointer main_function; struct ac_llvm_pointer main_function;
LLVMValueRef descriptor_sets[MAX_SETS];
LLVMValueRef gs_wave_id;
uint64_t output_mask;
}; };
static inline struct radv_shader_context * static inline struct radv_shader_context *
@ -85,29 +79,6 @@ create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module, LLVMBuil
return main_function; return main_function;
} }
static void
load_descriptor_sets(struct radv_shader_context *ctx)
{
const struct radv_userdata_locations *user_sgprs_locs = &ctx->shader_info->user_sgprs_locs;
uint32_t mask = ctx->shader_info->desc_set_used_mask;
if (user_sgprs_locs->shader_data[AC_UD_INDIRECT_DESCRIPTOR_SETS].sgpr_idx != -1) {
struct ac_llvm_pointer desc_sets = ac_get_ptr_arg(&ctx->ac, &ctx->args->ac, ctx->args->descriptor_sets[0]);
while (mask) {
int i = u_bit_scan(&mask);
ctx->descriptor_sets[i] = ac_build_load_to_sgpr(&ctx->ac, desc_sets, LLVMConstInt(ctx->ac.i32, i, false));
LLVMSetAlignment(ctx->descriptor_sets[i], 4);
}
} else {
while (mask) {
int i = u_bit_scan(&mask);
ctx->descriptor_sets[i] = ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
}
}
}
static enum ac_llvm_calling_convention static enum ac_llvm_calling_convention
get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage) get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
{ {
@ -155,8 +126,6 @@ create_function(struct radv_shader_context *ctx, gl_shader_stage stage, bool has
get_llvm_calling_convention(ctx->main_function.value, stage), get_llvm_calling_convention(ctx->main_function.value, stage),
ctx->max_workgroup_size, ctx->options); ctx->max_workgroup_size, ctx->options);
load_descriptor_sets(ctx);
if (stage == MESA_SHADER_TESS_CTRL || (stage == MESA_SHADER_VERTEX && ctx->shader_info->vs.as_ls) || if (stage == MESA_SHADER_TESS_CTRL || (stage == MESA_SHADER_VERTEX && ctx->shader_info->vs.as_ls) ||
ctx->shader_info->is_ngg || ctx->shader_info->is_ngg ||
/* GFX9 has the ESGS ring buffer in LDS. */ /* GFX9 has the ESGS ring buffer in LDS. */
@ -231,24 +200,6 @@ radv_get_sampler_desc(struct ac_shader_abi *abi, LLVMValueRef index, enum ac_des
return radv_load_rsrc(ctx, index, v4 ? ctx->ac.v4i32 : ctx->ac.v8i32); return radv_load_rsrc(ctx, index, v4 ? ctx->ac.v4i32 : ctx->ac.v8i32);
} }
static void
scan_shader_output_decl(struct radv_shader_context *ctx, struct nir_variable *variable, struct nir_shader *shader,
gl_shader_stage stage)
{
int idx = variable->data.driver_location;
unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
uint64_t mask_attribs;
if (variable->data.compact) {
unsigned component_count = variable->data.location_frac + glsl_get_length(variable->type);
attrib_count = (component_count + 3) / 4;
}
mask_attribs = ((1ull << attrib_count) - 1) << idx;
ctx->output_mask |= mask_attribs;
}
static LLVMValueRef static LLVMValueRef
radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan) radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
{ {
@ -266,16 +217,6 @@ ac_llvm_finalize_module(struct radv_shader_context *ctx, LLVMPassManagerRef pass
ac_llvm_context_dispose(&ctx->ac); ac_llvm_context_dispose(&ctx->ac);
} }
static void
prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
{
if (merged) {
ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.merged_wave_info), 16, 8);
} else {
ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->ac.gs_wave_id);
}
}
/* Ensure that the esgs ring is declared. /* Ensure that the esgs ring is declared.
* *
* We declare it with 64KB alignment as a hint that the * We declare it with 64KB alignment as a hint that the
@ -408,7 +349,6 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, const struct radv_nir
for (int shader_idx = 0; shader_idx < shader_count; ++shader_idx) { for (int shader_idx = 0; shader_idx < shader_count; ++shader_idx) {
ctx.stage = shaders[shader_idx]->info.stage; ctx.stage = shaders[shader_idx]->info.stage;
ctx.shader = shaders[shader_idx]; ctx.shader = shaders[shader_idx];
ctx.output_mask = 0;
if (shader_idx && !(shaders[shader_idx]->info.stage == MESA_SHADER_GEOMETRY && info->is_ngg)) { if (shader_idx && !(shaders[shader_idx]->info.stage == MESA_SHADER_GEOMETRY && info->is_ngg)) {
/* Execute a barrier before the second shader in /* Execute a barrier before the second shader in
@ -432,9 +372,6 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, const struct radv_nir
ac_build_s_barrier(&ctx.ac, shaders[shader_idx]->info.stage); ac_build_s_barrier(&ctx.ac, shaders[shader_idx]->info.stage);
} }
nir_foreach_shader_out_variable (variable, shaders[shader_idx])
scan_shader_output_decl(&ctx, variable, shaders[shader_idx], shaders[shader_idx]->info.stage);
bool check_merged_wave_info = shader_count >= 2 && !(is_ngg && shader_idx == 1); bool check_merged_wave_info = shader_count >= 2 && !(is_ngg && shader_idx == 1);
LLVMBasicBlockRef merge_block = NULL; LLVMBasicBlockRef merge_block = NULL;
@ -452,9 +389,6 @@ ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm, const struct radv_nir
LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block); LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
} }
if (shaders[shader_idx]->info.stage == MESA_SHADER_GEOMETRY && !info->is_ngg)
prepare_gs_input_vgprs(&ctx, shader_count >= 2);
if (!ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[shader_idx])) { if (!ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[shader_idx])) {
abort(); abort();
} }