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radeonsi/uvd_enc: Add VUI parameters in output bitstream

Browse source 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25991>
This commit is contained in:
David Rosca 2023-10-31 19:20:31 +01:00 • committed by Marge Bot
parent 72fadf5faf
commit af2980e5b9
3 changed files with 102 additions and 1 deletions
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32
src/gallium/drivers/radeonsi/radeon_uvd_enc.c
View file

@ -31,6 +31,37 @@
#define UVD_HEVC_LEVEL_6_1 183
#define UVD_HEVC_LEVEL_6_2 186
static void radeon_uvd_enc_get_vui_param(struct radeon_uvd_encoder *enc,
struct pipe_h265_enc_picture_desc *pic)
{
enc->enc_pic.vui_info.vui_parameters_present_flag =
pic->seq.vui_parameters_present_flag;
enc->enc_pic.vui_info.flags.aspect_ratio_info_present_flag =
pic->seq.vui_flags.aspect_ratio_info_present_flag;
enc->enc_pic.vui_info.flags.timing_info_present_flag =
pic->seq.vui_flags.timing_info_present_flag;
enc->enc_pic.vui_info.flags.video_signal_type_present_flag =
pic->seq.vui_flags.video_signal_type_present_flag;
enc->enc_pic.vui_info.flags.colour_description_present_flag =
pic->seq.vui_flags.colour_description_present_flag;
enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag =
pic->seq.vui_flags.chroma_loc_info_present_flag;
enc->enc_pic.vui_info.aspect_ratio_idc = pic->seq.aspect_ratio_idc;
enc->enc_pic.vui_info.sar_width = pic->seq.sar_width;
enc->enc_pic.vui_info.sar_height = pic->seq.sar_height;
enc->enc_pic.vui_info.num_units_in_tick = pic->seq.num_units_in_tick;
enc->enc_pic.vui_info.time_scale = pic->seq.time_scale;
enc->enc_pic.vui_info.video_format = pic->seq.video_format;
enc->enc_pic.vui_info.video_full_range_flag = pic->seq.video_full_range_flag;
enc->enc_pic.vui_info.colour_primaries = pic->seq.colour_primaries;
enc->enc_pic.vui_info.transfer_characteristics = pic->seq.transfer_characteristics;
enc->enc_pic.vui_info.matrix_coefficients = pic->seq.matrix_coefficients;
enc->enc_pic.vui_info.chroma_sample_loc_type_top_field =
pic->seq.chroma_sample_loc_type_top_field;
enc->enc_pic.vui_info.chroma_sample_loc_type_bottom_field =
pic->seq.chroma_sample_loc_type_bottom_field;
}
static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
struct pipe_h265_enc_picture_desc *pic)
{
@ -80,6 +111,7 @@ static void radeon_uvd_enc_get_param(struct radeon_uvd_encoder *enc,
enc->enc_pic.sample_adaptive_offset_enabled_flag = pic->seq.sample_adaptive_offset_enabled_flag;
enc->enc_pic.pcm_enabled_flag = 0; /*HW not support PCM */
enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
radeon_uvd_enc_get_vui_param(enc, pic);
}
static void flush(struct radeon_uvd_encoder *enc)

26
src/gallium/drivers/radeonsi/radeon_uvd_enc.h
View file

@ -303,6 +303,31 @@ typedef struct ruvd_enc_feedback_buffer_s {
uint32_t feedback_data_size;
} ruvd_enc_feedback_buffer_t;
typedef struct ruvd_enc_vui_info_s
{
uint32_t vui_parameters_present_flag;
struct {
uint32_t aspect_ratio_info_present_flag : 1;
uint32_t timing_info_present_flag : 1;
uint32_t video_signal_type_present_flag : 1;
uint32_t colour_description_present_flag : 1;
uint32_t chroma_loc_info_present_flag : 1;
} flags;
uint32_t aspect_ratio_idc;
uint32_t sar_width;
uint32_t sar_height;
uint32_t num_units_in_tick;
uint32_t time_scale;
uint32_t video_format;
uint32_t video_full_range_flag;
uint32_t colour_primaries;
uint32_t transfer_characteristics;
uint32_t matrix_coefficients;
uint32_t chroma_sample_loc_type_top_field;
uint32_t chroma_sample_loc_type_bottom_field;
uint32_t max_num_reorder_frames;
} ruvd_enc_vui_info;
typedef void (*radeon_uvd_enc_get_buffer)(struct pipe_resource *resource, struct pb_buffer **handle,
struct radeon_surf **surface);
@ -339,6 +364,7 @@ struct radeon_uvd_enc_pic {
unsigned bit_depth_chroma_minus8;
unsigned nal_unit_type;
unsigned max_num_merge_cand;
ruvd_enc_vui_info vui_info;
bool not_referenced;
bool is_iframe;

45
src/gallium/drivers/radeonsi/radeon_uvd_enc_1_1.c
View file

@ -451,7 +451,50 @@ static void radeon_uvd_enc_nalu_sps_hevc(struct radeon_uvd_encoder *enc)
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled,
1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.vui_parameters_present_flag), 1);
if (enc->enc_pic.vui_info.vui_parameters_present_flag) {
/* aspect ratio present flag */
radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.flags.aspect_ratio_info_present_flag), 1);
if (enc->enc_pic.vui_info.flags.aspect_ratio_info_present_flag) {
radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.aspect_ratio_idc), 8);
if (enc->enc_pic.vui_info.aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.sar_width), 16);
radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.sar_height), 16);
}
}
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* overscan info present flag */
/* video signal type present flag */
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.flags.video_signal_type_present_flag, 1);
if (enc->enc_pic.vui_info.flags.video_signal_type_present_flag) {
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.video_format, 3);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.video_full_range_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.flags.colour_description_present_flag, 1);
if (enc->enc_pic.vui_info.flags.colour_description_present_flag) {
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.colour_primaries, 8);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.transfer_characteristics, 8);
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.matrix_coefficients, 8);
}
}
/* chroma loc info present flag */
radeon_uvd_enc_code_fixed_bits(enc, enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag, 1);
if (enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag) {
radeon_uvd_enc_code_ue(enc, enc->enc_pic.vui_info.chroma_sample_loc_type_top_field);
radeon_uvd_enc_code_ue(enc, enc->enc_pic.vui_info.chroma_sample_loc_type_bottom_field);
}
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* default display windows flag */
/* vui timing info present flag */
radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.flags.timing_info_present_flag), 1);
if (enc->enc_pic.vui_info.flags.timing_info_present_flag) {
radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.num_units_in_tick), 32);
radeon_uvd_enc_code_fixed_bits(enc, (enc->enc_pic.vui_info.time_scale), 32);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
}
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1); /* bitstream restriction flag */
}
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);