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aco: swap opsel and wait_exp for vinterp

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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28435>
This commit is contained in:
Georg Lehmann 2024-04-03 18:21:35 +02:00 • committed by Marge Bot
parent 81a334a594
commit af199c6949
2 changed files with 12 additions and 12 deletions
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4
src/amd/compiler/aco_opcodes.py
View file

@ -186,8 +186,8 @@ class Format(IntEnum):
elif self == Format.VOPD:
return [('aco_opcode', 'opy', None)]
elif self == Format.VINTERP_INREG:
return [('unsigned', 'wait_exp', 7),
('uint8_t', 'opsel', 0)]
return [('uint8_t', 'opsel', 0),
('unsigned', 'wait_exp', 7)]
elif self in [Format.FLAT, Format.GLOBAL, Format.SCRATCH]:
return [('int16_t', 'offset', 0),
('memory_sync_info', 'sync', 'memory_sync_info()'),

20
src/amd/compiler/tests/test_assembler.cpp
View file

@ -796,43 +796,43 @@ BEGIN_TEST(assembler.gfx11.vinterp)
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2);
//! v_interp_p10_f32 v42, v10, v20, v30 wait_exp:6 ; cd00062a 047a290a
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 6);
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 0, 6);
//; if llvm_ver >= 18:
//; insert_pattern('v_interp_p2_f32 v42, v10, v20, v30 wait_exp:0 ; cd01002a 047a290a')
//; else:
//; insert_pattern('v_interp_p2_f32 v42, v10, v20, v30 ; cd01002a 047a290a')
bld.vinterp_inreg(aco_opcode::v_interp_p2_f32_inreg, dst, op0, op1, op2, 0);
bld.vinterp_inreg(aco_opcode::v_interp_p2_f32_inreg, dst, op0, op1, op2, 0, 0);
//! v_interp_p10_f32 v42, -v10, v20, v30 wait_exp:6 ; cd00062a 247a290a
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 6)
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 0, 6)
->vinterp_inreg()
.neg[0] = true;
//! v_interp_p10_f32 v42, v10, -v20, v30 wait_exp:6 ; cd00062a 447a290a
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 6)
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 0, 6)
->vinterp_inreg()
.neg[1] = true;
//! v_interp_p10_f32 v42, v10, v20, -v30 wait_exp:6 ; cd00062a 847a290a
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 6)
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 0, 6)
->vinterp_inreg()
.neg[2] = true;
//! v_interp_p10_f16_f32 v42, v10, v20, v30 op_sel:[1,0,0,0] wait_exp:6 ; cd020e2a 047a290a
bld.vinterp_inreg(aco_opcode::v_interp_p10_f16_f32_inreg, dst, op0, op1, op2, 6, 0x1);
bld.vinterp_inreg(aco_opcode::v_interp_p10_f16_f32_inreg, dst, op0, op1, op2, 0x1, 6);
//! v_interp_p2_f16_f32 v42, v10, v20, v30 op_sel:[0,1,0,0] wait_exp:6 ; cd03162a 047a290a
bld.vinterp_inreg(aco_opcode::v_interp_p2_f16_f32_inreg, dst, op0, op1, op2, 6, 0x2);
bld.vinterp_inreg(aco_opcode::v_interp_p2_f16_f32_inreg, dst, op0, op1, op2, 0x2, 6);
//! v_interp_p10_rtz_f16_f32 v42, v10, v20, v30 op_sel:[0,0,1,0] wait_exp:6 ; cd04262a 047a290a
bld.vinterp_inreg(aco_opcode::v_interp_p10_rtz_f16_f32_inreg, dst, op0, op1, op2, 6, 0x4);
bld.vinterp_inreg(aco_opcode::v_interp_p10_rtz_f16_f32_inreg, dst, op0, op1, op2, 0x4, 6);
//! v_interp_p2_rtz_f16_f32 v42, v10, v20, v30 op_sel:[0,0,0,1] wait_exp:6 ; cd05462a 047a290a
bld.vinterp_inreg(aco_opcode::v_interp_p2_rtz_f16_f32_inreg, dst, op0, op1, op2, 6, 0x8);
bld.vinterp_inreg(aco_opcode::v_interp_p2_rtz_f16_f32_inreg, dst, op0, op1, op2, 0x8, 6);
//! v_interp_p10_f32 v42, v10, v20, v30 clamp wait_exp:6 ; cd00862a 047a290a
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 6)
bld.vinterp_inreg(aco_opcode::v_interp_p10_f32_inreg, dst, op0, op1, op2, 0, 6)
->vinterp_inreg()
.clamp = true;