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ac/gpu_info: handle LPDDR4 and 5 in ac_memory_ops_per_clock

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and update amdgpu_drm.h

Fixes: 50238f4958 - amd/common: Remove redundant code for determining memory ops per clock
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7163

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18340>
This commit is contained in:
Marek Olšák 2022-08-28 20:50:42 -04:00 • committed by Marge Bot
parent c551bb32d1
commit aef7ea868f
2 changed files with 17 additions and 8 deletions
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6
include/drm-uapi/amdgpu_drm.h
View file

@ -559,6 +559,10 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_HW_IP_VCE 4 #define AMDGPU_HW_IP_VCE 4
#define AMDGPU_HW_IP_UVD_ENC 5 #define AMDGPU_HW_IP_UVD_ENC 5
#define AMDGPU_HW_IP_VCN_DEC 6 #define AMDGPU_HW_IP_VCN_DEC 6
/*
* From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support
* both encoding and decoding jobs.
*/
#define AMDGPU_HW_IP_VCN_ENC 7 #define AMDGPU_HW_IP_VCN_ENC 7
#define AMDGPU_HW_IP_VCN_JPEG 8 #define AMDGPU_HW_IP_VCN_JPEG 8
#define AMDGPU_HW_IP_NUM 9 #define AMDGPU_HW_IP_NUM 9
@ -994,6 +998,8 @@ struct drm_amdgpu_info_vbios {
#define AMDGPU_VRAM_TYPE_DDR4 8 #define AMDGPU_VRAM_TYPE_DDR4 8
#define AMDGPU_VRAM_TYPE_GDDR6 9 #define AMDGPU_VRAM_TYPE_GDDR6 9
#define AMDGPU_VRAM_TYPE_DDR5 10 #define AMDGPU_VRAM_TYPE_DDR5 10
#define AMDGPU_VRAM_TYPE_LPDDR4 11
#define AMDGPU_VRAM_TYPE_LPDDR5 12
struct drm_amdgpu_info_device { struct drm_amdgpu_info_device {
/** PCI Device ID */ /** PCI Device ID */

19
src/amd/common/ac_gpu_info.c
View file

@ -86,6 +86,8 @@
#define AMDGPU_VRAM_TYPE_DDR4 8 #define AMDGPU_VRAM_TYPE_DDR4 8
#define AMDGPU_VRAM_TYPE_GDDR6 9 #define AMDGPU_VRAM_TYPE_GDDR6 9
#define AMDGPU_VRAM_TYPE_DDR5 10 #define AMDGPU_VRAM_TYPE_DDR5 10
#define AMDGPU_VRAM_TYPE_LPDDR4 11
#define AMDGPU_VRAM_TYPE_LPDDR5 12
struct drm_amdgpu_heap_info { struct drm_amdgpu_heap_info {
uint64_t total_heap_size; uint64_t total_heap_size;
@ -1998,22 +2000,23 @@ uint32_t ac_memory_ops_per_clock(uint32_t vram_type)
{ {
/* Based on MemoryOpsPerClockTable from PAL. */ /* Based on MemoryOpsPerClockTable from PAL. */
switch (vram_type) { switch (vram_type) {
case AMDGPU_VRAM_TYPE_GDDR1:
case AMDGPU_VRAM_TYPE_GDDR3: /* last in low-end Evergreen */
case AMDGPU_VRAM_TYPE_GDDR4: /* last in R7xx, not used much */
case AMDGPU_VRAM_TYPE_UNKNOWN: case AMDGPU_VRAM_TYPE_UNKNOWN:
default:
return 0; return 0;
case AMDGPU_VRAM_TYPE_DDR2: case AMDGPU_VRAM_TYPE_DDR2:
case AMDGPU_VRAM_TYPE_DDR3: case AMDGPU_VRAM_TYPE_DDR3:
case AMDGPU_VRAM_TYPE_DDR4: /* same for LPDDR4 */ case AMDGPU_VRAM_TYPE_DDR4:
case AMDGPU_VRAM_TYPE_LPDDR4:
case AMDGPU_VRAM_TYPE_HBM: /* same for HBM2 and HBM3 */ case AMDGPU_VRAM_TYPE_HBM: /* same for HBM2 and HBM3 */
return 2; return 2;
case AMDGPU_VRAM_TYPE_DDR5: /* same for LPDDR5 */ case AMDGPU_VRAM_TYPE_DDR5:
case AMDGPU_VRAM_TYPE_GDDR5: case AMDGPU_VRAM_TYPE_LPDDR5:
case AMDGPU_VRAM_TYPE_GDDR5: /* last in Polaris and low-end Navi14 */
return 4; return 4;
case AMDGPU_VRAM_TYPE_GDDR6: case AMDGPU_VRAM_TYPE_GDDR6:
return 16; return 16;
case AMDGPU_VRAM_TYPE_GDDR1:
case AMDGPU_VRAM_TYPE_GDDR3:
case AMDGPU_VRAM_TYPE_GDDR4:
default:
unreachable("Invalid vram type");
} }
} }