diff --git a/src/gallium/drivers/crocus/crocus_program.c b/src/gallium/drivers/crocus/crocus_program.c index 296896083b9..5557999456b 100644 --- a/src/gallium/drivers/crocus/crocus_program.c +++ b/src/gallium/drivers/crocus/crocus_program.c @@ -2428,8 +2428,8 @@ crocus_update_compiled_shaders(struct crocus_context *ice) } else if (tes) { const struct brw_tes_prog_data *tes_data = (void *) tes->prog_data; points_or_lines = - tes_data->output_topology == BRW_TESS_OUTPUT_TOPOLOGY_LINE || - tes_data->output_topology == BRW_TESS_OUTPUT_TOPOLOGY_POINT; + tes_data->output_topology == INTEL_TESS_OUTPUT_TOPOLOGY_LINE || + tes_data->output_topology == INTEL_TESS_OUTPUT_TOPOLOGY_POINT; } if (ice->shaders.output_topology_is_points_or_lines != points_or_lines) { diff --git a/src/gallium/drivers/crocus/crocus_state.c b/src/gallium/drivers/crocus/crocus_state.c index d1c0a912b2a..e13159a2af1 100644 --- a/src/gallium/drivers/crocus/crocus_state.c +++ b/src/gallium/drivers/crocus/crocus_state.c @@ -4442,7 +4442,7 @@ crocus_is_drawing_points(const struct crocus_context *ice) } else if (ice->shaders.prog[MESA_SHADER_TESS_EVAL]) { const struct brw_tes_prog_data *tes_data = (void *) ice->shaders.prog[MESA_SHADER_TESS_EVAL]->prog_data; - return tes_data->output_topology == BRW_TESS_OUTPUT_TOPOLOGY_POINT; + return tes_data->output_topology == INTEL_TESS_OUTPUT_TOPOLOGY_POINT; } else { return ice->state.prim_mode == MESA_PRIM_POINTS; } @@ -7025,7 +7025,7 @@ crocus_upload_dirty_render_state(struct crocus_context *ice, ds.MaximumNumberofThreads = batch->screen->devinfo.max_tes_threads - 1; ds.ComputeWCoordinateEnable = - tes_prog_data->domain == BRW_TESS_DOMAIN_TRI; + tes_prog_data->domain == INTEL_TESS_DOMAIN_TRI; #if GFX_VER >= 8 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8) diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 2857a184cf5..62ae340f315 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -2165,8 +2165,8 @@ iris_update_compiled_shaders(struct iris_context *ice) } else if (tes) { const struct brw_tes_prog_data *tes_data = (void *) tes->prog_data; points_or_lines = - tes_data->output_topology == BRW_TESS_OUTPUT_TOPOLOGY_LINE || - tes_data->output_topology == BRW_TESS_OUTPUT_TOPOLOGY_POINT; + tes_data->output_topology == INTEL_TESS_OUTPUT_TOPOLOGY_LINE || + tes_data->output_topology == INTEL_TESS_OUTPUT_TOPOLOGY_POINT; } if (ice->shaders.output_topology_is_points_or_lines != points_or_lines) { diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 0c8779d7bb5..77ad2501ed7 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -4725,7 +4725,7 @@ iris_is_drawing_points(const struct iris_context *ice) } else if (ice->shaders.prog[MESA_SHADER_TESS_EVAL]) { const struct brw_tes_prog_data *tes_data = (void *) ice->shaders.prog[MESA_SHADER_TESS_EVAL]->prog_data; - return tes_data->output_topology == BRW_TESS_OUTPUT_TOPOLOGY_POINT; + return tes_data->output_topology == INTEL_TESS_OUTPUT_TOPOLOGY_POINT; } else { return ice->state.prim_mode == MESA_PRIM_POINTS; } @@ -5048,7 +5048,7 @@ iris_store_tes_state(const struct intel_device_info *devinfo, ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH; ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1; ds.ComputeWCoordinateEnable = - tes_prog_data->domain == BRW_TESS_DOMAIN_TRI; + tes_prog_data->domain == INTEL_TESS_DOMAIN_TRI; #if GFX_VER >= 12 ds.PrimitiveIDNotRequired = !tes_prog_data->include_primitive_id; diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index eac4251a6ca..d8262c20080 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -1485,34 +1485,6 @@ enum shader_dispatch_mode { DISPATCH_MODE_TCS_MULTI_PATCH = 2, }; -/** - * @defgroup Tessellator parameter enumerations. - * - * These correspond to the hardware values in 3DSTATE_TE, and are provided - * as part of the tessellation evaluation shader. - * - * @{ - */ -enum brw_tess_partitioning { - BRW_TESS_PARTITIONING_INTEGER = 0, - BRW_TESS_PARTITIONING_ODD_FRACTIONAL = 1, - BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2, -}; - -enum brw_tess_output_topology { - BRW_TESS_OUTPUT_TOPOLOGY_POINT = 0, - BRW_TESS_OUTPUT_TOPOLOGY_LINE = 1, - BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2, - BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3, -}; - -enum brw_tess_domain { - BRW_TESS_DOMAIN_QUAD = 0, - BRW_TESS_DOMAIN_TRI = 1, - BRW_TESS_DOMAIN_ISOLINE = 2, -}; -/** @} */ - struct brw_vue_prog_data { struct brw_stage_prog_data base; struct brw_vue_map vue_map; @@ -1570,9 +1542,9 @@ struct brw_tes_prog_data { struct brw_vue_prog_data base; - enum brw_tess_partitioning partitioning; - enum brw_tess_output_topology output_topology; - enum brw_tess_domain domain; + enum intel_tess_partitioning partitioning; + enum intel_tess_output_topology output_topology; + enum intel_tess_domain domain; bool include_primitive_id; }; diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index c500f5e2b4f..de90bc6c296 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1331,38 +1331,38 @@ brw_compile_tes(const struct brw_compiler *compiler, prog_data->base.urb_read_length = 0; - STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1); - STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL == + STATIC_ASSERT(INTEL_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1); + STATIC_ASSERT(INTEL_TESS_PARTITIONING_ODD_FRACTIONAL == TESS_SPACING_FRACTIONAL_ODD - 1); - STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL == + STATIC_ASSERT(INTEL_TESS_PARTITIONING_EVEN_FRACTIONAL == TESS_SPACING_FRACTIONAL_EVEN - 1); prog_data->partitioning = - (enum brw_tess_partitioning) (nir->info.tess.spacing - 1); + (enum intel_tess_partitioning) (nir->info.tess.spacing - 1); switch (nir->info.tess._primitive_mode) { case TESS_PRIMITIVE_QUADS: - prog_data->domain = BRW_TESS_DOMAIN_QUAD; + prog_data->domain = INTEL_TESS_DOMAIN_QUAD; break; case TESS_PRIMITIVE_TRIANGLES: - prog_data->domain = BRW_TESS_DOMAIN_TRI; + prog_data->domain = INTEL_TESS_DOMAIN_TRI; break; case TESS_PRIMITIVE_ISOLINES: - prog_data->domain = BRW_TESS_DOMAIN_ISOLINE; + prog_data->domain = INTEL_TESS_DOMAIN_ISOLINE; break; default: unreachable("invalid domain shader primitive mode"); } if (nir->info.tess.point_mode) { - prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT; + prog_data->output_topology = INTEL_TESS_OUTPUT_TOPOLOGY_POINT; } else if (nir->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES) { - prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE; + prog_data->output_topology = INTEL_TESS_OUTPUT_TOPOLOGY_LINE; } else { /* Hardware winding order is backwards from OpenGL */ prog_data->output_topology = - nir->info.tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW - : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW; + nir->info.tess.ccw ? INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CW + : INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CCW; } if (unlikely(debug_enabled)) { diff --git a/src/intel/compiler/brw_vec4_tes.cpp b/src/intel/compiler/brw_vec4_tes.cpp index b1107b44397..7af5220be75 100644 --- a/src/intel/compiler/brw_vec4_tes.cpp +++ b/src/intel/compiler/brw_vec4_tes.cpp @@ -122,7 +122,7 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) src_reg(brw_vec8_grf(1, 0)))); break; case nir_intrinsic_load_tess_level_outer: - if (tes_prog_data->domain == BRW_TESS_DOMAIN_ISOLINE) { + if (tes_prog_data->domain == INTEL_TESS_DOMAIN_ISOLINE) { emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F), swizzle(src_reg(ATTR, 1, glsl_vec4_type()), BRW_SWIZZLE_ZWZW))); @@ -133,7 +133,7 @@ vec4_tes_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) } break; case nir_intrinsic_load_tess_level_inner: - if (tes_prog_data->domain == BRW_TESS_DOMAIN_QUAD) { + if (tes_prog_data->domain == INTEL_TESS_DOMAIN_QUAD) { emit(MOV(get_nir_def(instr->def, BRW_REGISTER_TYPE_F), swizzle(src_reg(ATTR, 0, glsl_vec4_type()), BRW_SWIZZLE_WZYX))); diff --git a/src/intel/compiler/intel_shader_enums.h b/src/intel/compiler/intel_shader_enums.h index 0c4ae9d948b..58bffc88b2a 100644 --- a/src/intel/compiler/intel_shader_enums.h +++ b/src/intel/compiler/intel_shader_enums.h @@ -48,6 +48,34 @@ enum intel_msaa_flags { }; MESA_DEFINE_CPP_ENUM_BITFIELD_OPERATORS(intel_msaa_flags) +/** + * @defgroup Tessellator parameter enumerations. + * + * These correspond to the hardware values in 3DSTATE_TE, and are provided + * as part of the tessellation evaluation shader. + * + * @{ + */ +enum intel_tess_partitioning { + INTEL_TESS_PARTITIONING_INTEGER = 0, + INTEL_TESS_PARTITIONING_ODD_FRACTIONAL = 1, + INTEL_TESS_PARTITIONING_EVEN_FRACTIONAL = 2, +}; + +enum intel_tess_output_topology { + INTEL_TESS_OUTPUT_TOPOLOGY_POINT = 0, + INTEL_TESS_OUTPUT_TOPOLOGY_LINE = 1, + INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CW = 2, + INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3, +}; + +enum intel_tess_domain { + INTEL_TESS_DOMAIN_QUAD = 0, + INTEL_TESS_DOMAIN_TRI = 1, + INTEL_TESS_DOMAIN_ISOLINE = 2, +}; +/** @} */ + #ifdef __cplusplus } /* extern "C" */ #endif diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 87f2ec4d763..9d021960e03 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -727,14 +727,14 @@ genX(raster_polygon_mode)(const struct anv_graphics_pipeline *pipeline, unreachable("Unsupported GS output topology"); } else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) { switch (get_tes_prog_data(pipeline)->output_topology) { - case BRW_TESS_OUTPUT_TOPOLOGY_POINT: + case INTEL_TESS_OUTPUT_TOPOLOGY_POINT: return VK_POLYGON_MODE_POINT; - case BRW_TESS_OUTPUT_TOPOLOGY_LINE: + case INTEL_TESS_OUTPUT_TOPOLOGY_LINE: return VK_POLYGON_MODE_LINE; - case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW: - case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW: + case INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CW: + case INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CCW: return polygon_mode; } unreachable("Unsupported TCS output topology"); @@ -1344,7 +1344,7 @@ emit_3dstate_hs_ds(struct anv_graphics_pipeline *pipeline, ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1; ds.ComputeWCoordinateEnable = - tes_prog_data->domain == BRW_TESS_DOMAIN_TRI; + tes_prog_data->domain == INTEL_TESS_DOMAIN_TRI; ds.PatchURBEntryReadLength = tes_prog_data->base.urb_read_length; ds.PatchURBEntryReadOffset = 0; diff --git a/src/intel/vulkan_hasvk/genX_pipeline.c b/src/intel/vulkan_hasvk/genX_pipeline.c index 8e50f660c4c..cd9785711f0 100644 --- a/src/intel/vulkan_hasvk/genX_pipeline.c +++ b/src/intel/vulkan_hasvk/genX_pipeline.c @@ -476,14 +476,14 @@ genX(raster_polygon_mode)(struct anv_graphics_pipeline *pipeline, unreachable("Unsupported GS output topology"); } else if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) { switch (get_tes_prog_data(pipeline)->output_topology) { - case BRW_TESS_OUTPUT_TOPOLOGY_POINT: + case INTEL_TESS_OUTPUT_TOPOLOGY_POINT: return VK_POLYGON_MODE_POINT; - case BRW_TESS_OUTPUT_TOPOLOGY_LINE: + case INTEL_TESS_OUTPUT_TOPOLOGY_LINE: return VK_POLYGON_MODE_LINE; - case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW: - case BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW: + case INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CW: + case INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CCW: return pipeline->polygon_mode; } unreachable("Unsupported TCS output topology"); @@ -1437,7 +1437,7 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline, ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1; ds.ComputeWCoordinateEnable = - tes_prog_data->domain == BRW_TESS_DOMAIN_TRI; + tes_prog_data->domain == INTEL_TESS_DOMAIN_TRI; ds.PatchURBEntryReadLength = tes_prog_data->base.urb_read_length; ds.PatchURBEntryReadOffset = 0;