diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index e75110704c6..87ff6e443a1 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2629,9 +2629,12 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } case nir_op_unpack_half_2x16_split_x_flush_to_zero: case nir_op_unpack_half_2x16_split_x: { + Temp src = get_alu_src(ctx, instr->src[0]); + if (src.regClass() == v1) + src = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), src); if (dst.regClass() == v1) { assert(ctx->block->fp_mode.must_flush_denorms16_64 == (instr->op == nir_op_unpack_half_2x16_split_x_flush_to_zero)); - bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), get_alu_src(ctx, instr->src[0])); + bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), src); } else { isel_err(&instr->instr, "Unimplemented NIR instr bit size"); } @@ -2639,11 +2642,14 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } case nir_op_unpack_half_2x16_split_y_flush_to_zero: case nir_op_unpack_half_2x16_split_y: { + Temp src = get_alu_src(ctx, instr->src[0]); + if (src.regClass() == s1) + src = bld.sop2(aco_opcode::s_lshr_b32, bld.def(s1), bld.def(s1, scc), src, Operand(16u)); + else + src = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), src).def(1).getTemp(); if (dst.regClass() == v1) { assert(ctx->block->fp_mode.must_flush_denorms16_64 == (instr->op == nir_op_unpack_half_2x16_split_y_flush_to_zero)); - /* TODO: use SDWA here */ - bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), - bld.vop2(aco_opcode::v_lshrrev_b32, bld.def(v1), Operand(16u), as_vgpr(ctx, get_alu_src(ctx, instr->src[0])))); + bld.vop1(aco_opcode::v_cvt_f32_f16, Definition(dst), src); } else { isel_err(&instr->instr, "Unimplemented NIR instr bit size"); }