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r600: use rctx consistently in evergreen_compute.c
Another step towards cleaning this up. Acked-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
parent
0560c82ff6
commit
aeb2be3a2f
1 changed files with 74 additions and 74 deletions
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@ -254,7 +254,7 @@ static void r600_destroy_shader(struct r600_bytecode *bc)
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void *evergreen_create_compute_state(struct pipe_context *ctx_,
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const const struct pipe_compute_state *cso)
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{
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struct r600_context *ctx = (struct r600_context *)ctx_;
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struct r600_context *rctx = (struct r600_context *)ctx_;
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struct r600_pipe_compute *shader = CALLOC_STRUCT(r600_pipe_compute);
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#ifdef HAVE_OPENCL
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const struct pipe_llvm_program_header *header;
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@ -262,21 +262,21 @@ void *evergreen_create_compute_state(struct pipe_context *ctx_,
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void *p;
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boolean use_kill;
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COMPUTE_DBG(ctx->screen, "*** evergreen_create_compute_state\n");
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COMPUTE_DBG(rctx->screen, "*** evergreen_create_compute_state\n");
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header = cso->prog;
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code = cso->prog + sizeof(struct pipe_llvm_program_header);
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radeon_shader_binary_init(&shader->binary);
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radeon_elf_read(code, header->num_bytes, &shader->binary);
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r600_create_shader(&shader->bc, &shader->binary, &use_kill);
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shader->code_bo = r600_compute_buffer_alloc_vram(ctx->screen,
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shader->code_bo = r600_compute_buffer_alloc_vram(rctx->screen,
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shader->bc.ndw * 4);
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p = r600_buffer_map_sync_with_rings(&ctx->b, shader->code_bo, PIPE_TRANSFER_WRITE);
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p = r600_buffer_map_sync_with_rings(&rctx->b, shader->code_bo, PIPE_TRANSFER_WRITE);
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memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4);
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ctx->b.ws->buffer_unmap(shader->code_bo->buf);
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rctx->b.ws->buffer_unmap(shader->code_bo->buf);
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#endif
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shader->ctx = ctx;
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shader->ctx = rctx;
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shader->local_size = cso->req_local_mem;
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shader->private_size = cso->req_private_mem;
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shader->input_size = cso->req_input_mem;
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@ -286,10 +286,10 @@ void *evergreen_create_compute_state(struct pipe_context *ctx_,
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void evergreen_delete_compute_state(struct pipe_context *ctx_, void *state)
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{
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struct r600_context *ctx = (struct r600_context *)ctx_;
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struct r600_context *rctx = (struct r600_context *)ctx_;
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struct r600_pipe_compute *shader = state;
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COMPUTE_DBG(ctx->screen, "*** evergreen_delete_compute_state\n");
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COMPUTE_DBG(rctx->screen, "*** evergreen_delete_compute_state\n");
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if (!shader)
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return;
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@ -304,11 +304,11 @@ void evergreen_delete_compute_state(struct pipe_context *ctx_, void *state)
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static void evergreen_bind_compute_state(struct pipe_context *ctx_, void *state)
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{
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struct r600_context *ctx = (struct r600_context *)ctx_;
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struct r600_context *rctx = (struct r600_context *)ctx_;
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COMPUTE_DBG(ctx->screen, "*** evergreen_bind_compute_state\n");
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COMPUTE_DBG(rctx->screen, "*** evergreen_bind_compute_state\n");
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ctx->cs_shader_state.shader = (struct r600_pipe_compute *)state;
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rctx->cs_shader_state.shader = (struct r600_pipe_compute *)state;
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}
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/* The kernel parameters are stored a vtx buffer (ID=0), besides the explicit
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@ -327,8 +327,8 @@ void evergreen_compute_upload_input(struct pipe_context *ctx_,
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const uint *grid_layout,
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const void *input)
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{
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struct r600_context *ctx = (struct r600_context *)ctx_;
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struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
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struct r600_context *rctx = (struct r600_context *)ctx_;
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struct r600_pipe_compute *shader = rctx->cs_shader_state.shader;
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unsigned i;
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/* We need to reserve 9 dwords (36 bytes) for implicit kernel
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* parameters.
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@ -376,14 +376,14 @@ void evergreen_compute_upload_input(struct pipe_context *ctx_,
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memcpy(kernel_parameters_start, input, shader->input_size);
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for (i = 0; i < (input_size / 4); i++) {
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COMPUTE_DBG(ctx->screen, "input %i : %u\n", i,
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COMPUTE_DBG(rctx->screen, "input %i : %u\n", i,
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((unsigned*)num_work_groups_start)[i]);
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}
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ctx_->transfer_unmap(ctx_, transfer);
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/* ID=0 is reserved for the parameters */
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evergreen_cs_set_constant_buffer(ctx, 0, 0, input_size,
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evergreen_cs_set_constant_buffer(rctx, 0, 0, input_size,
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(struct pipe_resource*)shader->kernel_param);
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}
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@ -456,16 +456,16 @@ static void evergreen_emit_direct_dispatch(struct r600_context *rctx,
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radeon_emit(cs, 1);
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}
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static void compute_emit_cs(struct r600_context *ctx,
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static void compute_emit_cs(struct r600_context *rctx,
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const uint *block_layout,
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const uint *grid_layout)
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{
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struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
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struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
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unsigned i;
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/* make sure that the gfx ring is only one active */
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if (ctx->b.dma.cs && ctx->b.dma.cs->cdw) {
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ctx->b.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL);
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if (rctx->b.dma.cs && rctx->b.dma.cs->cdw) {
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rctx->b.dma.flush(rctx, RADEON_FLUSH_ASYNC, NULL);
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}
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/* Initialize all the compute-related registers.
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@ -473,20 +473,20 @@ static void compute_emit_cs(struct r600_context *ctx,
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* See evergreen_init_atom_start_compute_cs() in this file for the list
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* of registers initialized by the start_compute_cs_cmd atom.
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*/
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r600_emit_command_buffer(cs, &ctx->start_compute_cs_cmd);
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r600_emit_command_buffer(cs, &rctx->start_compute_cs_cmd);
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/* emit config state */
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if (ctx->b.chip_class == EVERGREEN)
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r600_emit_atom(ctx, &ctx->config_state.atom);
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if (rctx->b.chip_class == EVERGREEN)
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r600_emit_atom(rctx, &rctx->config_state.atom);
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ctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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r600_flush_emit(ctx);
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rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
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r600_flush_emit(rctx);
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/* Emit colorbuffers. */
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/* XXX support more than 8 colorbuffers (the offsets are not a multiple of 0x3C for CB8-11) */
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for (i = 0; i < 8 && i < ctx->framebuffer.state.nr_cbufs; i++) {
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struct r600_surface *cb = (struct r600_surface*)ctx->framebuffer.state.cbufs[i];
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unsigned reloc = radeon_add_to_buffer_list(&ctx->b, &ctx->b.gfx,
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for (i = 0; i < 8 && i < rctx->framebuffer.state.nr_cbufs; i++) {
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struct r600_surface *cb = (struct r600_surface*)rctx->framebuffer.state.cbufs[i];
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unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
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(struct r600_resource*)cb->base.texture,
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RADEON_USAGE_READWRITE,
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RADEON_PRIO_SHADER_RW_BUFFER);
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@ -515,37 +515,37 @@ static void compute_emit_cs(struct r600_context *ctx,
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/* Set CB_TARGET_MASK XXX: Use cb_misc_state */
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radeon_compute_set_context_reg(cs, R_028238_CB_TARGET_MASK,
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ctx->compute_cb_target_mask);
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rctx->compute_cb_target_mask);
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/* Emit vertex buffer state */
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ctx->cs_vertex_buffer_state.atom.num_dw = 12 * util_bitcount(ctx->cs_vertex_buffer_state.dirty_mask);
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r600_emit_atom(ctx, &ctx->cs_vertex_buffer_state.atom);
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rctx->cs_vertex_buffer_state.atom.num_dw = 12 * util_bitcount(rctx->cs_vertex_buffer_state.dirty_mask);
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r600_emit_atom(rctx, &rctx->cs_vertex_buffer_state.atom);
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/* Emit constant buffer state */
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r600_emit_atom(ctx, &ctx->constbuf_state[PIPE_SHADER_COMPUTE].atom);
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r600_emit_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom);
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/* Emit sampler state */
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r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].states.atom);
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r600_emit_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom);
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/* Emit sampler view (texture resource) state */
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r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].views.atom);
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r600_emit_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom);
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/* Emit compute shader state */
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r600_emit_atom(ctx, &ctx->cs_shader_state.atom);
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r600_emit_atom(rctx, &rctx->cs_shader_state.atom);
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/* Emit dispatch state and dispatch packet */
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evergreen_emit_direct_dispatch(ctx, block_layout, grid_layout);
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evergreen_emit_direct_dispatch(rctx, block_layout, grid_layout);
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/* XXX evergreen_flush_emit() hardcodes the CP_COHER_SIZE to 0xffffffff
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*/
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ctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
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rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
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R600_CONTEXT_INV_VERTEX_CACHE |
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R600_CONTEXT_INV_TEX_CACHE;
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r600_flush_emit(ctx);
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ctx->b.flags = 0;
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r600_flush_emit(rctx);
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rctx->b.flags = 0;
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if (ctx->b.chip_class >= CAYMAN) {
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if (rctx->b.chip_class >= CAYMAN) {
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cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
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cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4);
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/* DEALLOC_STATE prevents the GPU from hanging when a
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@ -557,9 +557,9 @@ static void compute_emit_cs(struct r600_context *ctx,
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}
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#if 0
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COMPUTE_DBG(ctx->screen, "cdw: %i\n", cs->cdw);
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COMPUTE_DBG(rctx->screen, "cdw: %i\n", cs->cdw);
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for (i = 0; i < cs->cdw; i++) {
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COMPUTE_DBG(ctx->screen, "%4i : 0x%08X\n", i, cs->buf[i]);
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COMPUTE_DBG(rctx->screen, "%4i : 0x%08X\n", i, cs->buf[i]);
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}
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#endif
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@ -601,32 +601,32 @@ void evergreen_emit_cs_shader(struct r600_context *rctx,
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static void evergreen_launch_grid(struct pipe_context *ctx_,
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const struct pipe_grid_info *info)
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{
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struct r600_context *ctx = (struct r600_context *)ctx_;
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struct r600_context *rctx = (struct r600_context *)ctx_;
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#ifdef HAVE_OPENCL
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struct r600_pipe_compute *shader = ctx->cs_shader_state.shader;
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struct r600_pipe_compute *shader = rctx->cs_shader_state.shader;
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boolean use_kill;
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ctx->cs_shader_state.pc = info->pc;
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rctx->cs_shader_state.pc = info->pc;
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/* Get the config information for this kernel. */
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r600_shader_binary_read_config(&shader->binary, &shader->bc,
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info->pc, &use_kill);
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#endif
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COMPUTE_DBG(ctx->screen, "*** evergreen_launch_grid: pc = %u\n", info->pc);
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COMPUTE_DBG(rctx->screen, "*** evergreen_launch_grid: pc = %u\n", info->pc);
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evergreen_compute_upload_input(ctx_, info->block, info->grid, info->input);
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compute_emit_cs(ctx, info->block, info->grid);
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compute_emit_cs(rctx, info->block, info->grid);
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}
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static void evergreen_set_compute_resources(struct pipe_context *ctx_,
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unsigned start, unsigned count,
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struct pipe_surface **surfaces)
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{
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struct r600_context *ctx = (struct r600_context *)ctx_;
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struct r600_context *rctx = (struct r600_context *)ctx_;
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struct r600_surface **resources = (struct r600_surface **)surfaces;
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COMPUTE_DBG(ctx->screen, "*** evergreen_set_compute_resources: start = %u count = %u\n",
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COMPUTE_DBG(rctx->screen, "*** evergreen_set_compute_resources: start = %u count = %u\n",
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start, count);
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for (unsigned i = 0; i < count; i++) {
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@ -640,13 +640,13 @@ static void evergreen_set_compute_resources(struct pipe_context *ctx_,
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if (resources[i]->base.writable) {
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assert(i+1 < 12);
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evergreen_set_rat(ctx->cs_shader_state.shader, i+1,
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evergreen_set_rat(rctx->cs_shader_state.shader, i+1,
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(struct r600_resource *)resources[i]->base.texture,
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buffer->chunk->start_in_dw*4,
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resources[i]->base.texture->width0);
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}
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evergreen_cs_set_vertex_buffer(ctx, vtx_id,
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evergreen_cs_set_vertex_buffer(rctx, vtx_id,
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buffer->chunk->start_in_dw * 4,
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resources[i]->base.texture);
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}
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@ -658,13 +658,13 @@ static void evergreen_set_global_binding(struct pipe_context *ctx_,
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struct pipe_resource **resources,
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uint32_t **handles)
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{
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struct r600_context *ctx = (struct r600_context *)ctx_;
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struct compute_memory_pool *pool = ctx->screen->global_pool;
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struct r600_context *rctx = (struct r600_context *)ctx_;
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struct compute_memory_pool *pool = rctx->screen->global_pool;
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struct r600_resource_global **buffers =
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(struct r600_resource_global **)resources;
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unsigned i;
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COMPUTE_DBG(ctx->screen, "*** evergreen_set_global_binding first = %u n = %u\n",
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COMPUTE_DBG(rctx->screen, "*** evergreen_set_global_binding first = %u n = %u\n",
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first, n);
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if (!resources) {
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@ -699,8 +699,8 @@ static void evergreen_set_global_binding(struct pipe_context *ctx_,
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*(handles[i]) = util_cpu_to_le32(handle);
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}
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evergreen_set_rat(ctx->cs_shader_state.shader, 0, pool->bo, 0, pool->size_in_dw * 4);
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evergreen_cs_set_vertex_buffer(ctx, 1, 0,
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evergreen_set_rat(rctx->cs_shader_state.shader, 0, pool->bo, 0, pool->size_in_dw * 4);
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evergreen_cs_set_vertex_buffer(rctx, 1, 0,
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(struct pipe_resource*)pool->bo);
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}
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@ -715,9 +715,9 @@ static void evergreen_set_global_binding(struct pipe_context *ctx_,
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* functions evergreen_init_atom_start_cs or cayman_init_atom_start_cs depending
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* on the GPU family.
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*/
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void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
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void evergreen_init_atom_start_compute_cs(struct r600_context *rctx)
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{
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struct r600_command_buffer *cb = &ctx->start_compute_cs_cmd;
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struct r600_command_buffer *cb = &rctx->start_compute_cs_cmd;
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int num_threads;
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int num_stack_entries;
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@ -736,7 +736,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
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r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0));
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r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
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switch (ctx->b.family) {
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switch (rctx->b.family) {
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case CHIP_CEDAR:
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default:
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num_threads = 128;
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@ -782,18 +782,18 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
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}
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/* Config Registers */
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if (ctx->b.chip_class < CAYMAN)
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evergreen_init_common_regs(ctx, cb, ctx->b.chip_class, ctx->b.family,
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ctx->screen->b.info.drm_minor);
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if (rctx->b.chip_class < CAYMAN)
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evergreen_init_common_regs(rctx, cb, rctx->b.chip_class, rctx->b.family,
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rctx->screen->b.info.drm_minor);
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else
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cayman_init_common_regs(cb, ctx->b.chip_class, ctx->b.family,
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ctx->screen->b.info.drm_minor);
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cayman_init_common_regs(cb, rctx->b.chip_class, rctx->b.family,
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rctx->screen->b.info.drm_minor);
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/* The primitive type always needs to be POINTLIST for compute. */
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r600_store_config_reg(cb, R_008958_VGT_PRIMITIVE_TYPE,
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V_008958_DI_PT_POINTLIST);
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if (ctx->b.chip_class < CAYMAN) {
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if (rctx->b.chip_class < CAYMAN) {
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/* These registers control which simds can be used by each stage.
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* The default for these registers is 0xffffffff, which means
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@ -843,7 +843,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
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* allocate the appropriate amount of LDS dwords using the
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* CM_R_0288E8_SQ_LDS_ALLOC register.
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*/
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if (ctx->b.chip_class < CAYMAN) {
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if (rctx->b.chip_class < CAYMAN) {
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r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
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S_008E2C_NUM_PS_LDS(0x0000) | S_008E2C_NUM_LS_LDS(8192));
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} else {
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@ -854,7 +854,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
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/* Context Registers */
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if (ctx->b.chip_class < CAYMAN) {
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if (rctx->b.chip_class < CAYMAN) {
|
||||
/* workaround for hw issues with dyn gpr - must set all limits
|
||||
* to 240 instead of 0, 0x1e == 240 / 8
|
||||
*/
|
||||
|
|
@ -896,15 +896,15 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx)
|
|||
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (160 * 4), 0x1000FFF);
|
||||
}
|
||||
|
||||
void evergreen_init_compute_state_functions(struct r600_context *ctx)
|
||||
void evergreen_init_compute_state_functions(struct r600_context *rctx)
|
||||
{
|
||||
ctx->b.b.create_compute_state = evergreen_create_compute_state;
|
||||
ctx->b.b.delete_compute_state = evergreen_delete_compute_state;
|
||||
ctx->b.b.bind_compute_state = evergreen_bind_compute_state;
|
||||
// ctx->context.create_sampler_view = evergreen_compute_create_sampler_view;
|
||||
ctx->b.b.set_compute_resources = evergreen_set_compute_resources;
|
||||
ctx->b.b.set_global_binding = evergreen_set_global_binding;
|
||||
ctx->b.b.launch_grid = evergreen_launch_grid;
|
||||
rctx->b.b.create_compute_state = evergreen_create_compute_state;
|
||||
rctx->b.b.delete_compute_state = evergreen_delete_compute_state;
|
||||
rctx->b.b.bind_compute_state = evergreen_bind_compute_state;
|
||||
// rctx->context.create_sampler_view = evergreen_compute_create_sampler_view;
|
||||
rctx->b.b.set_compute_resources = evergreen_set_compute_resources;
|
||||
rctx->b.b.set_global_binding = evergreen_set_global_binding;
|
||||
rctx->b.b.launch_grid = evergreen_launch_grid;
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue