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freedreno/registers: Improve A2D docs

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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42089>
This commit is contained in:
Rob Clark 2026-05-07 10:39:44 -07:00 • committed by Marge Bot
parent 88210dfcf5
commit aea956a25f
7 changed files with 828 additions and 813 deletions
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25
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2170,12 +2170,12 @@ by a particular renderpass/blit.
<bitfield name="SCISSOR" pos="16" type="boolean"/>
<bitfield name="UNK17" low="17" high="18"/>
<!-- required when blitting D24S8/D24X8 -->
<bitfield name="D24S8" pos="19" type="boolean"/>
<bitfield name="IS_SRC_YUV" pos="19" type="boolean"/>
<!-- some sort of channel mask, disabled channels are set to zero ? -->
<bitfield name="MASK" low="20" high="23"/>
<bitfield name="IFMT" low="24" high="26" type="a6xx_2d_ifmt"/>
<bitfield name="UNK27" pos="27" type="boolean"/>
<bitfield name="UNK28" pos="28" type="boolean"/>
<bitfield name="FULL_RANGE_YUV" pos="27" type="boolean"/>
<bitfield name="LINEAR_YUV" pos="28" type="boolean"/>
<bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>
<bitfield name="COPY" pos="30" type="boolean" variants="A7XX-"/>
</bitset>
@ -2761,7 +2761,22 @@ by a particular renderpass/blit.
<reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="draw"/>
<reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" usage="blit"/>
<reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="blit"/>
<enum name="a6xx_a2d_pixel_op">
<value value="0" name="PIXEL_OP_DISABLED"/>
<value value="1" name="PIXEL_OP_BLENDING"/>
<value value="3" name="PIXEL_OP_ROP"/>
</enum>
<reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="blit">
<bitfield name="PIXEL_OP" low="0" high="1" type="a6xx_a2d_pixel_op"/>
<bitfield name="COLOR_SRC_FACTOR" low="6" high="10" type="adreno_rb_blend_factor"/>
<bitfield name="COLOR_BLEND_OP" low="11" high="13" type="a3xx_rb_blend_opcode"/>
<bitfield name="COLOR_DST_FACTOR" low="14" high="18" type="adreno_rb_blend_factor"/>
<bitfield name="ALPHA_SRC_FACTOR" low="19" high="23" type="adreno_rb_blend_factor"/>
<bitfield name="ALPHA_BLEND_OP" low="24" high="26" type="a3xx_rb_blend_opcode"/>
<bitfield name="ALPHA_DST_FACTOR" low="27" high="31" type="adreno_rb_blend_factor"/>
</reg32>
<bitset name="a6xx_a2d_src_texture_info" inline="yes">
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
@ -2814,7 +2829,7 @@ by a particular renderpass/blit.
<reg32 offset="0x8c2e" name="RB_A2D_CLEAR_COLOR_DW2" usage="blit"/>
<reg32 offset="0x8c2f" name="RB_A2D_CLEAR_COLOR_DW3" usage="blit"/>
<reg32 offset="0x8c34" name="RB_A2D_UNKNOWN_8C34" variants="A7XX-" usage="blit"/>
<reg32 offset="0x8c34" name="RB_A2D_DEST_BUFFER_ARRAY_PITCH" variants="A7XX-" usage="blit"/>
<!-- 0x8c35-0x8dff invalid -->

4
src/freedreno/tests/reference/crash.log
View file

@ -5774,7 +5774,7 @@ WARNING: 64b discontinuity (no _LO dword for 8910)
00000000 RB_COLOR_FLAG_BUFFER[0x7].ADDR: 0
00000000 RB_COLOR_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED }
00000000 RB_A2D_PIXEL_CNTL: 0
00000000 RB_A2D_PIXEL_CNTL: { PIXEL_OP = PIXEL_OP_DISABLED | COLOR_SRC_FACTOR = FACTOR_ZERO | COLOR_BLEND_OP = BLEND_DST_PLUS_SRC | COLOR_DST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OP = BLEND_DST_PLUS_SRC | ALPHA_DST_FACTOR = FACTOR_ZERO }
00000000 0x8c08: 00000000
00000000 0x8c09: 00000000
00000000 0x8c0a: 00000000
@ -5951,7 +5951,7 @@ WARNING: 64b discontinuity (no _LO dword for 8910)
00000000 RB_COLOR_FLAG_BUFFER[0x7].ADDR: 0
00000000 RB_COLOR_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED }
00000000 RB_A2D_PIXEL_CNTL: 0
00000000 RB_A2D_PIXEL_CNTL: { PIXEL_OP = PIXEL_OP_DISABLED | COLOR_SRC_FACTOR = FACTOR_ZERO | COLOR_BLEND_OP = BLEND_DST_PLUS_SRC | COLOR_DST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OP = BLEND_DST_PLUS_SRC | ALPHA_DST_FACTOR = FACTOR_ZERO }
00000000 0x8c08: 00000000
00000000 0x8c09: 00000000
00000000 0x8c0a: 00000000

1592
src/freedreno/tests/reference/crash_prefetch.log
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File diff suppressed because it is too large Load diff

12
src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
View file

@ -232,13 +232,13 @@ cmdstream[0]: 265 dwords
opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
0000000001058274: 0000: 70268000
write RB_A2D_PIXEL_CNTL (8c01)
RB_A2D_PIXEL_CNTL: 0
RB_A2D_PIXEL_CNTL: { PIXEL_OP = PIXEL_OP_DISABLED | COLOR_SRC_FACTOR = FACTOR_ZERO | COLOR_BLEND_OP = BLEND_DST_PLUS_SRC | COLOR_DST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OP = BLEND_DST_PLUS_SRC | ALPHA_DST_FACTOR = FACTOR_ZERO }
0000000001058278: 0000: 488c0101 00000000
write RB_A2D_BLT_CNTL (8c00)
RB_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | UNK28 | RASTER_MODE = TYPE_TILED }
RB_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | LINEAR_YUV | RASTER_MODE = TYPE_TILED }
0000000001058280: 0000: 408c0001 10f03080
write GRAS_A2D_BLT_CNTL (8400)
GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | UNK28 | RASTER_MODE = TYPE_TILED }
GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | LINEAR_YUV | RASTER_MODE = TYPE_TILED }
0000000001058288: 0000: 48840001 10f03080
write SP_A2D_OUTPUT_INFO (acc0)
SP_A2D_OUTPUT_INFO: { IFMT_TYPE = OUTPUT_IFMT_2D_FLOAT | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf }
@ -277,7 +277,7 @@ cmdstream[0]: 265 dwords
+? 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 }
+? 00000000 GRAS_LRZ_CNTL: { DIR = 0 }
+? 00000000 GRAS_MODE_CNTL: 0
!+ 10f03080 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | UNK28 | RASTER_MODE = TYPE_TILED }
!+ 10f03080 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | LINEAR_YUV | RASTER_MODE = TYPE_TILED }
+ 00000000 GRAS_A2D_DEST_TL: { X = 0 | Y = 0 }
!+ 00ff00ff GRAS_A2D_DEST_BR: { X = 255 | Y = 255 }
!+? 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS }
@ -295,8 +295,8 @@ cmdstream[0]: 265 dwords
+? 00000000 RB_UNKNOWN_881E: 0
+? 00000000 RB_LRZ_CNTL: { 0 }
+? 00000000 RB_UNKNOWN_88F0: 0
!+ 10f03080 RB_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | UNK28 | RASTER_MODE = TYPE_TILED }
+ 00000000 RB_A2D_PIXEL_CNTL: 0
!+ 10f03080 RB_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | LINEAR_YUV | RASTER_MODE = TYPE_TILED }
+ 00000000 RB_A2D_PIXEL_CNTL: { PIXEL_OP = PIXEL_OP_DISABLED | COLOR_SRC_FACTOR = FACTOR_ZERO | COLOR_BLEND_OP = BLEND_DST_PLUS_SRC | COLOR_DST_FACTOR = FACTOR_ZERO | ALPHA_SRC_FACTOR = FACTOR_ZERO | ALPHA_BLEND_OP = BLEND_DST_PLUS_SRC | ALPHA_DST_FACTOR = FACTOR_ZERO }
!+ 00001330 RB_A2D_DEST_BUFFER_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
!+ 01013000 RB_A2D_DEST_BUFFER_BASE: 0x1013000
!+ 00000010 RB_A2D_DEST_BUFFER_PITCH: 1024

4
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -507,7 +507,7 @@ r2d_setup_common(struct tu_cmd_buffer *cmd,
.solid_color = clear,
.color_format = fmt,
.scissor = scissor,
.d24s8 = fmt == FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 && !clear,
.is_src_yuv = fmt == FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 && !clear,
.mask = 0xf,
.ifmt = util_format_is_srgb(dst_format) ? R2D_UNORM8_SRGB : ifmt,
));
@ -517,7 +517,7 @@ r2d_setup_common(struct tu_cmd_buffer *cmd,
.solid_color = clear,
.color_format = fmt,
.scissor = scissor,
.d24s8 = fmt == FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 && !clear,
.is_src_yuv = fmt == FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 && !clear,
.mask = 0xf,
.ifmt = util_format_is_srgb(dst_format) ? R2D_UNORM8_SRGB : ifmt,
));

2
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -2415,7 +2415,7 @@ tu_init_hw_rp(struct tu_cs *cs)
{
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, VPC_UNKNOWN_CNTL(CHIP));
tu_cs_emit_regs(cs, RB_A2D_UNKNOWN_8C34(CHIP));
tu_cs_emit_regs(cs, RB_A2D_DEST_BUFFER_ARRAY_PITCH(CHIP));
}
}
TU_GENX(tu_init_hw_rp);

2
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
View file

@ -926,7 +926,7 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs)
ncrb.add(RB_UNKNOWN_8E09(CHIP, 0x7));
if (CHIP >= A7XX)
ncrb.add(RB_A2D_UNKNOWN_8C34(CHIP));
ncrb.add(RB_A2D_DEST_BUFFER_ARRAY_PITCH(CHIP));
}
/**