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iris/state: Move reg/mem load/store functions earlier in file
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Jordan Justen
Kenneth Graunke
parent
c84bd2b095
commit
ae9c311b9a
1 changed files with 122 additions and 124 deletions
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@ -487,6 +487,128 @@ _iris_emit_lrr(struct iris_batch *batch, uint32_t dst, uint32_t src)
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}
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}
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static void
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iris_load_register_reg32(struct iris_batch *batch, uint32_t dst,
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uint32_t src)
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{
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_iris_emit_lrr(batch, dst, src);
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}
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static void
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iris_load_register_reg64(struct iris_batch *batch, uint32_t dst,
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uint32_t src)
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{
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_iris_emit_lrr(batch, dst, src);
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_iris_emit_lrr(batch, dst + 4, src + 4);
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}
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static void
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iris_load_register_imm32(struct iris_batch *batch, uint32_t reg,
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uint32_t val)
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{
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_iris_emit_lri(batch, reg, val);
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}
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static void
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iris_load_register_imm64(struct iris_batch *batch, uint32_t reg,
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uint64_t val)
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{
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_iris_emit_lri(batch, reg + 0, val & 0xffffffff);
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_iris_emit_lri(batch, reg + 4, val >> 32);
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}
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/**
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* Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
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*/
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static void
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iris_load_register_mem32(struct iris_batch *batch, uint32_t reg,
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struct iris_bo *bo, uint32_t offset)
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{
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iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
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lrm.RegisterAddress = reg;
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lrm.MemoryAddress = ro_bo(bo, offset);
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}
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}
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/**
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* Load a 64-bit value from a buffer into a MMIO register via
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* two MI_LOAD_REGISTER_MEM commands.
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*/
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static void
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iris_load_register_mem64(struct iris_batch *batch, uint32_t reg,
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struct iris_bo *bo, uint32_t offset)
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{
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iris_load_register_mem32(batch, reg + 0, bo, offset + 0);
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iris_load_register_mem32(batch, reg + 4, bo, offset + 4);
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}
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static void
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iris_store_register_mem32(struct iris_batch *batch, uint32_t reg,
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struct iris_bo *bo, uint32_t offset,
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bool predicated)
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{
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iris_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
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srm.RegisterAddress = reg;
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srm.MemoryAddress = rw_bo(bo, offset);
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srm.PredicateEnable = predicated;
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}
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}
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static void
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iris_store_register_mem64(struct iris_batch *batch, uint32_t reg,
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struct iris_bo *bo, uint32_t offset,
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bool predicated)
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{
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iris_store_register_mem32(batch, reg + 0, bo, offset + 0, predicated);
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iris_store_register_mem32(batch, reg + 4, bo, offset + 4, predicated);
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}
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static void
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iris_store_data_imm32(struct iris_batch *batch,
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struct iris_bo *bo, uint32_t offset,
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uint32_t imm)
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{
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iris_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) {
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sdi.Address = rw_bo(bo, offset);
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sdi.ImmediateData = imm;
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}
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}
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static void
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iris_store_data_imm64(struct iris_batch *batch,
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struct iris_bo *bo, uint32_t offset,
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uint64_t imm)
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{
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/* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
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* 2 in genxml but it's actually variable length and we need 5 DWords.
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*/
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void *map = iris_get_command_space(batch, 4 * 5);
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_iris_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) {
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sdi.DWordLength = 5 - 2;
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sdi.Address = rw_bo(bo, offset);
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sdi.ImmediateData = imm;
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}
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}
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static void
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iris_copy_mem_mem(struct iris_batch *batch,
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struct iris_bo *dst_bo, uint32_t dst_offset,
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struct iris_bo *src_bo, uint32_t src_offset,
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unsigned bytes)
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{
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/* MI_COPY_MEM_MEM operates on DWords. */
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assert(bytes % 4 == 0);
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assert(dst_offset % 4 == 0);
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assert(src_offset % 4 == 0);
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for (unsigned i = 0; i < bytes; i += 4) {
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iris_emit_cmd(batch, GENX(MI_COPY_MEM_MEM), cp) {
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cp.DestinationMemoryAddress = rw_bo(dst_bo, dst_offset + i);
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cp.SourceMemoryAddress = ro_bo(src_bo, src_offset + i);
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}
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}
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}
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static void
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emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline)
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{
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@ -6108,130 +6230,6 @@ iris_rebind_buffer(struct iris_context *ice,
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/* ------------------------------------------------------------------- */
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static void
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iris_load_register_reg32(struct iris_batch *batch, uint32_t dst,
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uint32_t src)
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{
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_iris_emit_lrr(batch, dst, src);
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}
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static void
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iris_load_register_reg64(struct iris_batch *batch, uint32_t dst,
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uint32_t src)
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{
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_iris_emit_lrr(batch, dst, src);
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_iris_emit_lrr(batch, dst + 4, src + 4);
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}
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static void
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iris_load_register_imm32(struct iris_batch *batch, uint32_t reg,
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uint32_t val)
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{
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_iris_emit_lri(batch, reg, val);
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}
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static void
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iris_load_register_imm64(struct iris_batch *batch, uint32_t reg,
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uint64_t val)
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{
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_iris_emit_lri(batch, reg + 0, val & 0xffffffff);
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_iris_emit_lri(batch, reg + 4, val >> 32);
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}
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/**
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* Emit MI_LOAD_REGISTER_MEM to load a 32-bit MMIO register from a buffer.
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*/
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static void
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iris_load_register_mem32(struct iris_batch *batch, uint32_t reg,
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struct iris_bo *bo, uint32_t offset)
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{
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iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
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lrm.RegisterAddress = reg;
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lrm.MemoryAddress = ro_bo(bo, offset);
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}
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}
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/**
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* Load a 64-bit value from a buffer into a MMIO register via
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* two MI_LOAD_REGISTER_MEM commands.
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*/
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static void
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iris_load_register_mem64(struct iris_batch *batch, uint32_t reg,
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struct iris_bo *bo, uint32_t offset)
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{
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iris_load_register_mem32(batch, reg + 0, bo, offset + 0);
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iris_load_register_mem32(batch, reg + 4, bo, offset + 4);
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}
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static void
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iris_store_register_mem32(struct iris_batch *batch, uint32_t reg,
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struct iris_bo *bo, uint32_t offset,
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bool predicated)
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{
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iris_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
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srm.RegisterAddress = reg;
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srm.MemoryAddress = rw_bo(bo, offset);
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srm.PredicateEnable = predicated;
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}
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}
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static void
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iris_store_register_mem64(struct iris_batch *batch, uint32_t reg,
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struct iris_bo *bo, uint32_t offset,
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bool predicated)
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{
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iris_store_register_mem32(batch, reg + 0, bo, offset + 0, predicated);
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iris_store_register_mem32(batch, reg + 4, bo, offset + 4, predicated);
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}
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static void
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iris_store_data_imm32(struct iris_batch *batch,
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struct iris_bo *bo, uint32_t offset,
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uint32_t imm)
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{
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iris_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) {
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sdi.Address = rw_bo(bo, offset);
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sdi.ImmediateData = imm;
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}
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}
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static void
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iris_store_data_imm64(struct iris_batch *batch,
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struct iris_bo *bo, uint32_t offset,
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uint64_t imm)
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{
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/* Can't use iris_emit_cmd because MI_STORE_DATA_IMM has a length of
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* 2 in genxml but it's actually variable length and we need 5 DWords.
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*/
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void *map = iris_get_command_space(batch, 4 * 5);
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_iris_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) {
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sdi.DWordLength = 5 - 2;
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sdi.Address = rw_bo(bo, offset);
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sdi.ImmediateData = imm;
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}
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}
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static void
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iris_copy_mem_mem(struct iris_batch *batch,
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struct iris_bo *dst_bo, uint32_t dst_offset,
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struct iris_bo *src_bo, uint32_t src_offset,
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unsigned bytes)
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{
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/* MI_COPY_MEM_MEM operates on DWords. */
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assert(bytes % 4 == 0);
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assert(dst_offset % 4 == 0);
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assert(src_offset % 4 == 0);
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for (unsigned i = 0; i < bytes; i += 4) {
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iris_emit_cmd(batch, GENX(MI_COPY_MEM_MEM), cp) {
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cp.DestinationMemoryAddress = rw_bo(dst_bo, dst_offset + i);
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cp.SourceMemoryAddress = ro_bo(src_bo, src_offset + i);
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}
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}
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}
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/* ------------------------------------------------------------------- */
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static unsigned
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flags_to_post_sync_op(uint32_t flags)
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{
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