diff --git a/src/amd/vulkan/meta/radv_meta.c b/src/amd/vulkan/meta/radv_meta.c
index 52ff677c4f0..463502a92f4 100644
--- a/src/amd/vulkan/meta/radv_meta.c
+++ b/src/amd/vulkan/meta/radv_meta.c
@@ -100,58 +100,77 @@ radv_resume_queries(const struct radv_meta_saved_state *state, struct radv_cmd_b
 }
 
 void
-radv_meta_save(struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_buffer, uint32_t flags)
+radv_meta_begin(struct radv_cmd_buffer *cmd_buffer)
 {
-   VkPipelineBindPoint bind_point =
-      flags & RADV_META_SAVE_GRAPHICS_PIPELINE ? VK_PIPELINE_BIND_POINT_GRAPHICS : VK_PIPELINE_BIND_POINT_COMPUTE;
-   struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, bind_point);
+   struct radv_meta_saved_state *state = &cmd_buffer->state.meta;
 
-   assert(flags & (RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_COMPUTE_PIPELINE));
+   state->flags = 0;
+
+   for (unsigned i = 0; i <= MESA_SHADER_MESH; i++)
+      state->old_shader_objs[i] = cmd_buffer->state.shader_objs[i];
 
-   state->flags = flags;
    state->active_occlusion_queries = 0;
    state->active_emulated_prims_gen_queries = 0;
    state->active_emulated_prims_xfb_queries = 0;
 
-   if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE) {
-      assert(!(state->flags & RADV_META_SAVE_COMPUTE_PIPELINE));
+   radv_suspend_queries(state, cmd_buffer);
 
+   assert(!state->inside_meta_op);
+   state->inside_meta_op = true;
+}
+
+void
+radv_meta_save(struct radv_cmd_buffer *cmd_buffer, uint32_t flags)
+{
+   struct radv_meta_saved_state *state = &cmd_buffer->state.meta;
+
+   assert(state->inside_meta_op);
+
+   uint32_t save_flags = flags & ~state->flags;
+   state->flags |= flags;
+
+   if (save_flags & RADV_META_SAVE_GRAPHICS_PIPELINE) {
       state->old_graphics_pipeline = cmd_buffer->state.graphics_pipeline;
 
       /* Save all dynamic states. */
       state->dynamic = cmd_buffer->state.dynamic;
    }
 
-   if (state->flags & RADV_META_SAVE_COMPUTE_PIPELINE) {
-      assert(!(state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE));
-
+   if (save_flags & RADV_META_SAVE_COMPUTE_PIPELINE)
       state->old_compute_pipeline = cmd_buffer->state.compute_pipeline;
-   }
 
-   for (unsigned i = 0; i <= MESA_SHADER_MESH; i++) {
-      state->old_shader_objs[i] = cmd_buffer->state.shader_objs[i];
-   }
-
-   if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
-      state->old_descriptor_set0 = descriptors_state->sets[0];
-      state->old_descriptor_set0_valid = !!(descriptors_state->valid & 0x1);
+   if (save_flags & RADV_META_SAVE_DESCRIPTOR_BUFFER_ADDR0)
       state->old_descriptor_buffer_addr0 = cmd_buffer->descriptor_buffers[0];
-      state->old_descriptor_buffer0 = descriptors_state->descriptor_buffers[0];
+
+   if (save_flags & RADV_META_SAVE_GRAPHICS_DESCRIPTORS) {
+      struct radv_descriptor_state *descriptors_state =
+         radv_get_descriptors_state(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS);
+
+      state->graphics_descriptors.old_descriptor_set0 = descriptors_state->sets[0];
+      state->graphics_descriptors.old_descriptor_set0_valid = !!(descriptors_state->valid & 0x1);
+      state->graphics_descriptors.old_descriptor_buffer0 = descriptors_state->descriptor_buffers[0];
    }
 
-   if (state->flags & RADV_META_SAVE_CONSTANTS) {
+   if (save_flags & RADV_META_SAVE_COMPUTE_DESCRIPTORS) {
+      struct radv_descriptor_state *descriptors_state =
+         radv_get_descriptors_state(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE);
+
+      state->compute_descriptors.old_descriptor_set0 = descriptors_state->sets[0];
+      state->compute_descriptors.old_descriptor_set0_valid = !!(descriptors_state->valid & 0x1);
+      state->compute_descriptors.old_descriptor_buffer0 = descriptors_state->descriptor_buffers[0];
+   }
+
+   if (save_flags & RADV_META_SAVE_CONSTANTS)
       memcpy(state->push_constants, cmd_buffer->push_constants, MAX_PUSH_CONSTANTS_SIZE);
-   }
-
-   radv_suspend_queries(state, cmd_buffer);
 }
 
 void
-radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_buffer)
+radv_meta_end(struct radv_cmd_buffer *cmd_buffer)
 {
-   VkPipelineBindPoint bind_point = state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE ? VK_PIPELINE_BIND_POINT_GRAPHICS
-                                                                                    : VK_PIPELINE_BIND_POINT_COMPUTE;
-   struct radv_descriptor_state *descriptors_state = radv_get_descriptors_state(cmd_buffer, bind_point);
+   struct radv_meta_saved_state *state = &cmd_buffer->state.meta;
+
+   assert(state->inside_meta_op);
+   state->inside_meta_op = false;
 
    if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE) {
       if (state->old_graphics_pipeline) {
@@ -190,19 +209,39 @@ radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buf
       radv_CmdBindShadersEXT(radv_cmd_buffer_to_handle(cmd_buffer), stage_count, stages, shaders);
    }
 
-   if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
-      if (state->old_descriptor_set0_valid)
-         radv_set_descriptor_set(cmd_buffer, bind_point, state->old_descriptor_set0, 0);
+   if (state->flags & RADV_META_SAVE_DESCRIPTOR_BUFFER_ADDR0)
       cmd_buffer->descriptor_buffers[0] = state->old_descriptor_buffer_addr0;
-      descriptors_state->descriptor_buffers[0] = state->old_descriptor_buffer0;
+
+   if (state->flags & RADV_META_SAVE_GRAPHICS_DESCRIPTORS) {
+      struct radv_descriptor_state *descriptors_state =
+         radv_get_descriptors_state(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS);
+      if (state->graphics_descriptors.old_descriptor_set0_valid) {
+         radv_set_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
+                                 state->graphics_descriptors.old_descriptor_set0, 0);
+      }
+      descriptors_state->descriptor_buffers[0] = state->graphics_descriptors.old_descriptor_buffer0;
+   }
+
+   if (state->flags & RADV_META_SAVE_COMPUTE_DESCRIPTORS) {
+      struct radv_descriptor_state *descriptors_state =
+         radv_get_descriptors_state(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE);
+      if (state->compute_descriptors.old_descriptor_set0_valid) {
+         radv_set_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
+                                 state->compute_descriptors.old_descriptor_set0, 0);
+      }
+      descriptors_state->descriptor_buffers[0] = state->compute_descriptors.old_descriptor_buffer0;
    }
 
    if (state->flags & RADV_META_SAVE_CONSTANTS) {
-      VkShaderStageFlags stage_flags = VK_SHADER_STAGE_COMPUTE_BIT;
+      VkShaderStageFlags stage_flags = 0;
 
+      if (state->flags & RADV_META_SAVE_COMPUTE_PIPELINE)
+         stage_flags |= VK_SHADER_STAGE_COMPUTE_BIT;
       if (state->flags & RADV_META_SAVE_GRAPHICS_PIPELINE)
          stage_flags |= VK_SHADER_STAGE_ALL_GRAPHICS;
 
+      assert(stage_flags);
+
       const VkPushConstantsInfoKHR pc_info = {
          .sType = VK_STRUCTURE_TYPE_PUSH_CONSTANTS_INFO_KHR,
          .layout = VK_NULL_HANDLE,
@@ -366,6 +405,10 @@ radv_meta_bind_descriptors(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoi
    if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set_layout->size, &upload_offset, (void *)&ptr))
       return;
 
+   radv_meta_save(cmd_buffer, (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ? RADV_META_SAVE_GRAPHICS_DESCRIPTORS
+                                                                             : RADV_META_SAVE_COMPUTE_DESCRIPTORS) |
+                                 RADV_META_SAVE_DESCRIPTOR_BUFFER_ADDR0);
+
    for (uint32_t i = 0; i < num_descriptors; i++) {
       const VkDescriptorGetInfoEXT *descriptor = &descriptors[i];
       const uint32_t binding_offset = set_layout->binding[i].offset;
diff --git a/src/amd/vulkan/meta/radv_meta.h b/src/amd/vulkan/meta/radv_meta.h
index 245c35ad324..98296756fec 100644
--- a/src/amd/vulkan/meta/radv_meta.h
+++ b/src/amd/vulkan/meta/radv_meta.h
@@ -35,31 +35,11 @@ extern "C" {
 
 enum radv_meta_save_flags {
    RADV_META_SAVE_CONSTANTS = (1 << 0),
-   RADV_META_SAVE_DESCRIPTORS = (1 << 1),
-   RADV_META_SAVE_GRAPHICS_PIPELINE = (1 << 2),
-   RADV_META_SAVE_COMPUTE_PIPELINE = (1 << 3),
-};
-
-struct radv_meta_saved_state {
-   uint32_t flags;
-
-   struct radv_descriptor_set *old_descriptor_set0;
-   bool old_descriptor_set0_valid;
-   uint64_t old_descriptor_buffer_addr0;
-   uint64_t old_descriptor_buffer0;
-
-   struct radv_graphics_pipeline *old_graphics_pipeline;
-   struct radv_compute_pipeline *old_compute_pipeline;
-   struct radv_dynamic_state dynamic;
-
-   struct radv_shader_object *old_shader_objs[MESA_VULKAN_SHADER_STAGES];
-
-   char push_constants[MAX_PUSH_CONSTANTS_SIZE];
-
-   unsigned active_emulated_pipeline_queries;
-   unsigned active_emulated_prims_gen_queries;
-   unsigned active_emulated_prims_xfb_queries;
-   unsigned active_occlusion_queries;
+   RADV_META_SAVE_DESCRIPTOR_BUFFER_ADDR0 = (1 << 1),
+   RADV_META_SAVE_GRAPHICS_DESCRIPTORS = (1 << 2),
+   RADV_META_SAVE_COMPUTE_DESCRIPTORS = (1 << 3),
+   RADV_META_SAVE_GRAPHICS_PIPELINE = (1 << 4),
+   RADV_META_SAVE_COMPUTE_PIPELINE = (1 << 5),
 };
 
 enum radv_copy_flags {
@@ -130,19 +110,25 @@ void radv_device_finish_meta(struct radv_device *device);
 VkResult radv_device_init_accel_struct_build_state(struct radv_device *device);
 void radv_device_finish_accel_struct_build_state(struct radv_device *device);
 
-void radv_meta_save(struct radv_meta_saved_state *saved_state, struct radv_cmd_buffer *cmd_buffer, uint32_t flags);
+void radv_meta_begin(struct radv_cmd_buffer *cmd_buffer);
 
-void radv_meta_restore(const struct radv_meta_saved_state *state, struct radv_cmd_buffer *cmd_buffer);
+void radv_meta_save(struct radv_cmd_buffer *cmd_buffer, uint32_t flags);
 
+void radv_meta_end(struct radv_cmd_buffer *cmd_buffer);
+
+/* Helpers that save the correct state. */
 static inline void
 radv_meta_bind_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer, VkPipeline pipeline)
 {
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
    radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
 }
 
 static inline void
 radv_meta_set_viewport(struct radv_cmd_buffer *cmd_buffer, float x, float y, float width, float height)
 {
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
+
    VkViewport viewport = {
       .x = x,
       .y = y,
@@ -158,6 +144,8 @@ radv_meta_set_viewport(struct radv_cmd_buffer *cmd_buffer, float x, float y, flo
 static inline void
 radv_meta_set_scissor(struct radv_cmd_buffer *cmd_buffer, int32_t x, int32_t y, int32_t width, int32_t height)
 {
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
+
    VkRect2D scissor = {
       .offset.x = x,
       .offset.y = y,
@@ -179,18 +167,23 @@ radv_meta_set_viewport_and_scissor(struct radv_cmd_buffer *cmd_buffer, int32_t x
 static inline void
 radv_meta_set_sample_locations(struct radv_cmd_buffer *cmd_buffer, const VkSampleLocationsInfoEXT *sample_locs)
 {
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
+
    radv_CmdSetSampleLocationsEXT(radv_cmd_buffer_to_handle(cmd_buffer), sample_locs);
 }
 
 static inline void
 radv_meta_set_stencil_reference(struct radv_cmd_buffer *cmd_buffer, VkStencilFaceFlags face_mask, uint32_t reference)
 {
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
+
    radv_CmdSetStencilReference(radv_cmd_buffer_to_handle(cmd_buffer), face_mask, reference);
 }
 
 static inline void
 radv_meta_bind_compute_pipeline(struct radv_cmd_buffer *cmd_buffer, VkPipeline pipeline)
 {
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE);
    radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
 }
 
@@ -198,6 +191,8 @@ static inline void
 radv_meta_push_constants(struct radv_cmd_buffer *cmd_buffer, VkPipelineLayout layout, VkShaderStageFlags stage,
                          uint32_t offset, uint32_t size, const void *data)
 {
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_CONSTANTS);
+
    const VkPushConstantsInfoKHR push_constants_info = {
       .sType = VK_STRUCTURE_TYPE_PUSH_CONSTANTS_INFO,
       .layout = layout,
diff --git a/src/amd/vulkan/meta/radv_meta_astc_decode.c b/src/amd/vulkan/meta/radv_meta_astc_decode.c
index fc5b08e9319..4cc867bf63c 100644
--- a/src/amd/vulkan/meta/radv_meta_astc_decode.c
+++ b/src/amd/vulkan/meta/radv_meta_astc_decode.c
@@ -98,9 +98,6 @@ radv_meta_decode_astc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
                       const VkImageSubresourceLayers *subresource, VkOffset3D offset, VkExtent3D extent)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
 
    const bool is_3d = image->vk.image_type == VK_IMAGE_TYPE_3D;
    const uint32_t base_slice = is_3d ? offset.z : subresource->baseArrayLayer;
@@ -126,6 +123,4 @@ radv_meta_decode_astc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
 
    radv_image_view_finish(&src_iview);
    radv_image_view_finish(&dst_iview);
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
diff --git a/src/amd/vulkan/meta/radv_meta_blit.c b/src/amd/vulkan/meta/radv_meta_blit.c
index 05d99d69c2b..e366a130634 100644
--- a/src/amd/vulkan/meta/radv_meta_blit.c
+++ b/src/amd/vulkan/meta/radv_meta_blit.c
@@ -362,7 +362,6 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, VkI
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const VkImageSubresourceLayers *src_res = &region->srcSubresource;
    const VkImageSubresourceLayers *dst_res = &region->dstSubresource;
-   struct radv_meta_saved_state saved_state;
    struct radv_sampler sampler;
 
    /* From the Vulkan 1.0 spec:
@@ -383,9 +382,6 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, VkI
                         .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
                      });
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
-
    unsigned dst_start, dst_end;
    if (dst_image->vk.image_type == VK_IMAGE_TYPE_3D) {
       assert(dst_res->baseArrayLayer == 0);
@@ -520,8 +516,6 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image, VkI
       radv_image_view_finish(&src_iview);
    }
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    radv_sampler_finish(device, &sampler);
 }
 
@@ -534,10 +528,14 @@ radv_CmdBlitImage2(VkCommandBuffer commandBuffer, const VkBlitImageInfo2 *pBlitI
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    for (unsigned r = 0; r < pBlitImageInfo->regionCount; r++) {
       blit_image(cmd_buffer, src_image, pBlitImageInfo->srcImageLayout, dst_image, pBlitImageInfo->dstImageLayout,
                  &pBlitImageInfo->pRegions[r], pBlitImageInfo->filter);
    }
 
+   radv_meta_end(cmd_buffer);
+
    radv_resume_conditional_rendering(cmd_buffer);
 }
diff --git a/src/amd/vulkan/meta/radv_meta_buffer.c b/src/amd/vulkan/meta/radv_meta_buffer.c
index 6cc5fbbd980..2844504e4eb 100644
--- a/src/amd/vulkan/meta/radv_meta_buffer.c
+++ b/src/amd/vulkan/meta/radv_meta_buffer.c
@@ -151,7 +151,6 @@ static void
 radv_compute_fill_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size, uint32_t data)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    VkPipelineLayout layout;
    VkPipeline pipeline;
    VkResult result;
@@ -162,8 +161,6 @@ radv_compute_fill_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64
       return;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    assert(size <= UINT32_MAX);
@@ -185,8 +182,6 @@ radv_compute_fill_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64
    radv_meta_push_constants(cmd_buffer, layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(fill_consts), &fill_consts);
 
    radv_unaligned_dispatch(cmd_buffer, dim_x, 1, 1);
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 static void
@@ -194,7 +189,6 @@ radv_compute_copy_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, ui
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const bool use_16B_copy = size >= 16 && radv_is_copy_memory_4B_aligned(src_va, dst_va, size);
-   struct radv_meta_saved_state saved_state;
    VkPipelineLayout layout;
    VkPipeline pipeline;
    VkResult result;
@@ -205,8 +199,6 @@ radv_compute_copy_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, ui
       return;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    assert(size <= UINT32_MAX);
@@ -228,8 +220,6 @@ radv_compute_copy_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, ui
    radv_meta_push_constants(cmd_buffer, layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(copy_consts), &copy_consts);
 
    radv_unaligned_dispatch(cmd_buffer, dim_x, 1, 1);
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 static bool
@@ -330,10 +320,14 @@ radv_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSi
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    fillSize = vk_buffer_range(&dst_buffer->vk, dstOffset, fillSize) & ~3ull;
 
    radv_fill_buffer(cmd_buffer, dst_buffer->bo, vk_buffer_address(&dst_buffer->vk, dstOffset), fillSize, data);
 
+   radv_meta_end(cmd_buffer);
+
    radv_resume_conditional_rendering(cmd_buffer);
 }
 
@@ -369,6 +363,8 @@ radv_CmdCopyBuffer2(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2 *pCop
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    radv_cs_add_buffer(device->ws, cs->b, src_buffer->bo);
    radv_cs_add_buffer(device->ws, cs->b, dst_buffer->bo);
 
@@ -380,6 +376,8 @@ radv_CmdCopyBuffer2(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2 *pCop
       radv_copy_memory(cmd_buffer, src_va, dst_va, region->size, src_copy_flags, dst_copy_flags);
    }
 
+   radv_meta_end(cmd_buffer);
+
    radv_resume_conditional_rendering(cmd_buffer);
 }
 
@@ -440,9 +438,13 @@ radv_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDevice
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    radv_cs_add_buffer(device->ws, cs->b, dst_buffer->bo);
 
    radv_update_memory(cmd_buffer, dst_va, dataSize, pData, dst_copy_flags);
 
+   radv_meta_end(cmd_buffer);
+
    radv_resume_conditional_rendering(cmd_buffer);
 }
diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c
index 6673ac80cc8..d4012644f64 100644
--- a/src/amd/vulkan/meta/radv_meta_clear.c
+++ b/src/amd/vulkan/meta/radv_meta_clear.c
@@ -603,7 +603,6 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    struct radv_cmd_stream *cs = cmd_buffer->cs;
    uint64_t block_count = DIV_ROUND_UP(size, 1024);
-   struct radv_meta_saved_state saved_state;
    VkPipelineLayout layout;
    VkPipeline pipeline;
    VkResult result;
@@ -616,8 +615,6 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
 
    radv_cs_add_buffer(device->ws, cs->b, bo);
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    const unsigned constants[4] = {
@@ -631,8 +628,6 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
 
    radv_CmdDispatchBase(radv_cmd_buffer_to_handle(cmd_buffer), 0, 0, 0, block_count, 1, 1);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    return RADV_CMD_FLAG_CS_PARTIAL_FLUSH | radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
                                                                  VK_ACCESS_2_SHADER_WRITE_BIT, 0, image, NULL);
 }
@@ -991,7 +986,6 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, struct radv_im
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    unsigned bytes_per_pixel = vk_format_get_blocksize(image->vk.format);
    unsigned layer_count = vk_image_subresource_layer_count(&image->vk, range);
-   struct radv_meta_saved_state saved_state;
    bool is_msaa = image->vk.samples > 1;
    struct radv_image_view iview;
    VkPipelineLayout layout;
@@ -1025,9 +1019,6 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, struct radv_im
       return 0;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, range); l++) {
@@ -1091,8 +1082,6 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer, struct radv_im
       radv_image_view_finish(&iview);
    }
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    return RADV_CMD_FLAG_CS_PARTIAL_FLUSH | radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
                                                                  VK_ACCESS_2_SHADER_WRITE_BIT, 0, image, NULL);
 }
@@ -1626,7 +1615,6 @@ void
 radv_cmd_buffer_clear_rendering(struct radv_cmd_buffer *cmd_buffer, const VkRenderingInfo *pRenderingInfo)
 {
    const struct radv_rendering_state *render = &cmd_buffer->state.render;
-   struct radv_meta_saved_state saved_state;
    enum radv_cmd_flush_bits pre_flush = 0;
    enum radv_cmd_flush_bits post_flush = 0;
 
@@ -1635,7 +1623,7 @@ radv_cmd_buffer_clear_rendering(struct radv_cmd_buffer *cmd_buffer, const VkRend
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
 
    assert(render->color_att_count == pRenderingInfo->colorAttachmentCount);
    for (uint32_t i = 0; i < render->color_att_count; i++) {
@@ -1674,7 +1662,7 @@ radv_cmd_buffer_clear_rendering(struct radv_cmd_buffer *cmd_buffer, const VkRend
       }
    }
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
    cmd_buffer->state.flush_bits |= post_flush;
 
    radv_resume_conditional_rendering(cmd_buffer);
@@ -1903,24 +1891,17 @@ radv_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image_h, VkImageL
 {
    VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
    VK_FROM_HANDLE(radv_image, image, image_h);
-   struct radv_meta_saved_state saved_state;
    bool cs;
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
    cs = cmd_buffer->qf == RADV_QUEUE_COMPUTE || !radv_image_is_renderable(image);
 
-   enum radv_meta_save_flags save_flags = RADV_META_SAVE_CONSTANTS;
-   if (cs)
-      save_flags |= RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_DESCRIPTORS;
-   else
-      save_flags |= RADV_META_SAVE_GRAPHICS_PIPELINE;
-
-   radv_meta_save(&saved_state, cmd_buffer, save_flags);
+   radv_meta_begin(cmd_buffer);
 
    radv_cmd_clear_image(cmd_buffer, image, imageLayout, (const VkClearValue *)pColor, rangeCount, pRanges, cs);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
 
    radv_resume_conditional_rendering(cmd_buffer);
 }
@@ -1932,16 +1913,15 @@ radv_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image_h, V
 {
    VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
    VK_FROM_HANDLE(radv_image, image, image_h);
-   struct radv_meta_saved_state saved_state;
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
 
    radv_cmd_clear_image(cmd_buffer, image, imageLayout, (const VkClearValue *)pDepthStencil, rangeCount, pRanges,
                         false);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
 
    radv_resume_conditional_rendering(cmd_buffer);
 }
@@ -1951,11 +1931,10 @@ radv_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount
                          uint32_t rectCount, const VkClearRect *pRects)
 {
    VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
-   struct radv_meta_saved_state saved_state;
    enum radv_cmd_flush_bits pre_flush = 0;
    enum radv_cmd_flush_bits post_flush = 0;
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
 
    /* FINISHME: We can do better than this dumb loop. It thrashes too much
     * state.
@@ -1967,6 +1946,6 @@ radv_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount
       }
    }
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
    cmd_buffer->state.flush_bits |= post_flush;
 }
diff --git a/src/amd/vulkan/meta/radv_meta_clear_hiz.c b/src/amd/vulkan/meta/radv_meta_clear_hiz.c
index e26404e81c6..52950ddb146 100644
--- a/src/amd/vulkan/meta/radv_meta_clear_hiz.c
+++ b/src/amd/vulkan/meta/radv_meta_clear_hiz.c
@@ -93,7 +93,6 @@ radv_clear_hiz(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, con
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radeon_surf *surf = &image->planes[0].surface;
-   struct radv_meta_saved_state saved_state;
    struct radv_image_view iview;
    VkPipelineLayout layout;
    VkPipeline pipeline;
@@ -108,9 +107,6 @@ radv_clear_hiz(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, con
       return 0;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_CONSTANTS);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    const uint32_t base_width = surf->u.gfx9.zs.hiz.width_in_tiles;
@@ -164,8 +160,6 @@ radv_clear_hiz(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, con
       }
    }
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    return RADV_CMD_FLAG_CS_PARTIAL_FLUSH | radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
                                                                  VK_ACCESS_2_SHADER_WRITE_BIT, 0, image, range);
 }
diff --git a/src/amd/vulkan/meta/radv_meta_copy.c b/src/amd/vulkan/meta/radv_meta_copy.c
index 47d88c74691..bebb701f70b 100644
--- a/src/amd/vulkan/meta/radv_meta_copy.c
+++ b/src/amd/vulkan/meta/radv_meta_copy.c
@@ -193,17 +193,12 @@ gfx_or_compute_copy_memory_to_image(struct radv_cmd_buffer *cmd_buffer, uint64_t
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radv_physical_device *pdev = radv_device_physical(device);
-   struct radv_meta_saved_state saved_state;
 
    /* The Vulkan 1.0 spec says "dstImage must have a sample count equal to
     * VK_SAMPLE_COUNT_1_BIT."
     */
    assert(image->vk.samples == 1);
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  (use_compute ? RADV_META_SAVE_COMPUTE_PIPELINE : RADV_META_SAVE_GRAPHICS_PIPELINE) |
-                     RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
-
    if (use_compute) {
       radv_fixup_copy_dst_htile_metadata(cmd_buffer, image, layout, &region->imageSubresource, &region->imageOffset,
                                          &region->imageExtent, true);
@@ -293,8 +288,6 @@ gfx_or_compute_copy_memory_to_image(struct radv_cmd_buffer *cmd_buffer, uint64_t
       radv_fixup_copy_dst_htile_metadata(cmd_buffer, image, layout, &region->imageSubresource, &region->imageOffset,
                                          &region->imageExtent, false);
    }
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 VKAPI_ATTR void VKAPI_CALL
@@ -311,6 +304,8 @@ radv_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer, const VkCopyBufferToIm
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    radv_cs_add_buffer(device->ws, cs->b, src_buffer->bo);
 
    for (unsigned r = 0; r < pCopyBufferToImageInfo->regionCount; r++) {
@@ -354,6 +349,8 @@ radv_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer, const VkCopyBufferToIm
       }
    }
 
+   radv_meta_end(cmd_buffer);
+
    radv_resume_conditional_rendering(cmd_buffer);
 }
 
@@ -364,10 +361,6 @@ compute_copy_image_to_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t buffer
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radv_physical_device *pdev = radv_device_physical(device);
-   struct radv_meta_saved_state saved_state;
-
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
 
    /**
     * From the Vulkan 1.0.6 spec: 18.3 Copying Data Between Images
@@ -443,8 +436,6 @@ compute_copy_image_to_memory(struct radv_cmd_buffer *cmd_buffer, uint64_t buffer
       else
          slice_array++;
    }
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 VKAPI_ATTR void VKAPI_CALL
@@ -460,6 +451,8 @@ radv_CmdCopyImageToBuffer2(VkCommandBuffer commandBuffer, const VkCopyImageToBuf
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    radv_cs_add_buffer(device->ws, cs->b, dst_buffer->bo);
 
    for (unsigned r = 0; r < pCopyImageToBufferInfo->regionCount; r++) {
@@ -478,6 +471,8 @@ radv_CmdCopyImageToBuffer2(VkCommandBuffer commandBuffer, const VkCopyImageToBuf
       }
    }
 
+   radv_meta_end(cmd_buffer);
+
    radv_resume_conditional_rendering(cmd_buffer);
 }
 
@@ -565,7 +560,6 @@ gfx_or_compute_copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radv_physical_device *pdev = radv_device_physical(device);
-   struct radv_meta_saved_state saved_state;
 
    /* From the Vulkan 1.0 spec:
     *
@@ -582,10 +576,6 @@ gfx_or_compute_copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image
    assert(src_image->plane_count == 1 || util_is_power_of_two_nonzero(region->srcSubresource.aspectMask));
    assert(dst_image->plane_count == 1 || util_is_power_of_two_nonzero(region->dstSubresource.aspectMask));
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  (use_compute ? RADV_META_SAVE_COMPUTE_PIPELINE : RADV_META_SAVE_GRAPHICS_PIPELINE) |
-                     RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
-
    if (use_compute) {
       radv_fixup_copy_dst_htile_metadata(cmd_buffer, dst_image, dst_image_layout, &region->dstSubresource,
                                          &region->dstOffset, &region->extent, true);
@@ -690,8 +680,6 @@ gfx_or_compute_copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image
       radv_fixup_copy_dst_htile_metadata(cmd_buffer, dst_image, dst_image_layout, &region->dstSubresource,
                                          &region->dstOffset, &region->extent, true);
    }
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 VKAPI_ATTR void VKAPI_CALL
@@ -706,6 +694,8 @@ radv_CmdCopyImage2(VkCommandBuffer commandBuffer, const VkCopyImageInfo2 *pCopyI
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    for (unsigned r = 0; r < pCopyImageInfo->regionCount; r++) {
       const VkImageCopy2 *region = &pCopyImageInfo->pRegions[r];
       const VkImageAspectFlags src_aspect_mask = region->srcSubresource.aspectMask;
@@ -754,5 +744,7 @@ radv_CmdCopyImage2(VkCommandBuffer commandBuffer, const VkCopyImageInfo2 *pCopyI
       }
    }
 
+   radv_meta_end(cmd_buffer);
+
    radv_resume_conditional_rendering(cmd_buffer);
 }
diff --git a/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c b/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
index ab454c7dd85..a0324f305d3 100644
--- a/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
+++ b/src/amd/vulkan/meta/radv_meta_copy_vrs_htile.c
@@ -77,7 +77,6 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *
                     struct radv_image *dst_image, uint64_t htile_va, bool read_htile_value)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    VkPipelineLayout layout;
    VkPipeline pipeline;
    VkResult result;
@@ -94,9 +93,6 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *
       radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT, VK_ACCESS_2_SHADER_READ_BIT, 0, NULL,
                             NULL);
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    radv_meta_bind_descriptors(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 1,
@@ -127,8 +123,6 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *
 
    radv_unaligned_dispatch(cmd_buffer, width, height, 1);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
                                    radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
                                                          VK_ACCESS_2_SHADER_WRITE_BIT, 0, NULL, NULL);
diff --git a/src/amd/vulkan/meta/radv_meta_dcc_retile.c b/src/amd/vulkan/meta/radv_meta_dcc_retile.c
index 0d837125c01..3045eefe6cb 100644
--- a/src/amd/vulkan/meta/radv_meta_dcc_retile.c
+++ b/src/amd/vulkan/meta/radv_meta_dcc_retile.c
@@ -108,7 +108,6 @@ get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *p
 void
 radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
 {
-   struct radv_meta_saved_state saved_state;
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    struct radv_cmd_stream *cs = cmd_buffer->cs;
    VkPipelineLayout layout;
@@ -129,9 +128,6 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
    state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT,
                                               VK_ACCESS_2_SHADER_READ_BIT, 0, image, NULL);
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    const uint64_t va = image->bindings[0].addr;
@@ -181,8 +177,6 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
 
    radv_unaligned_dispatch(cmd_buffer, dcc_width, dcc_height, 1);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    state->flush_bits |=
       RADV_CMD_FLAG_CS_PARTIAL_FLUSH | radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
                                                              VK_ACCESS_2_SHADER_WRITE_BIT, 0, image, NULL);
diff --git a/src/amd/vulkan/meta/radv_meta_decompress.c b/src/amd/vulkan/meta/radv_meta_decompress.c
index b61b5178460..515be985c59 100644
--- a/src/amd/vulkan/meta/radv_meta_decompress.c
+++ b/src/amd/vulkan/meta/radv_meta_decompress.c
@@ -214,7 +214,6 @@ radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image
                            const VkImageSubresourceRange *subresourceRange, const VkSampleLocationsInfoEXT *sample_locs)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    VkPipelineLayout layout;
    VkPipeline pipeline;
    VkResult result;
@@ -225,8 +224,6 @@ radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image
       return;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
-
    radv_meta_bind_graphics_pipeline(cmd_buffer, pipeline);
 
    if (sample_locs) {
@@ -254,8 +251,6 @@ radv_process_depth_stencil(struct radv_cmd_buffer *cmd_buffer, struct radv_image
          radv_process_depth_image_layer(cmd_buffer, image, subresourceRange, l, s);
       }
    }
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 static VkResult
@@ -327,7 +322,6 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
                                   const VkImageSubresourceRange *subresourceRange)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    struct radv_image_view load_iview = {0};
    struct radv_image_view store_iview = {0};
    VkPipelineLayout layout;
@@ -342,8 +336,6 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
       return;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); l++) {
@@ -427,8 +419,6 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
          radv_image_view_finish(&store_iview);
       }
    }
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 void
diff --git a/src/amd/vulkan/meta/radv_meta_etc_decode.c b/src/amd/vulkan/meta/radv_meta_etc_decode.c
index 7f28bf1e204..b5f99fcc94a 100644
--- a/src/amd/vulkan/meta/radv_meta_etc_decode.c
+++ b/src/amd/vulkan/meta/radv_meta_etc_decode.c
@@ -72,9 +72,6 @@ radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
                      const VkImageSubresourceLayers *subresource, VkOffset3D offset, VkExtent3D extent)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
 
    const bool is_3d = image->vk.image_type == VK_IMAGE_TYPE_3D;
    const uint32_t base_slice = is_3d ? offset.z : subresource->baseArrayLayer;
@@ -144,6 +141,4 @@ radv_meta_decode_etc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
 
    radv_image_view_finish(&src_iview);
    radv_image_view_finish(&dst_iview);
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c
index b1ccba6eb06..f2d63868aed 100644
--- a/src/amd/vulkan/meta/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c
@@ -322,7 +322,6 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radv_physical_device *pdev = radv_device_physical(device);
-   struct radv_meta_saved_state saved_state;
    bool old_predicating = false;
    uint64_t pred_offset;
    VkPipelineLayout layout;
@@ -359,8 +358,6 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
       pred_offset = 0;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
-
    if (pred_offset) {
       pred_offset += 8 * subresourceRange->baseMipLevel;
 
@@ -408,8 +405,6 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
       }
    }
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    /* Clear the image's fast-clear eliminate predicate because FMASK_DECOMPRESS and DCC_DECOMPRESS
     * also perform a fast-clear eliminate.
     */
@@ -455,7 +450,6 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
                             const VkImageSubresourceRange *subresourceRange)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    struct radv_image_view load_iview = {0};
    struct radv_image_view store_iview = {0};
    VkPipelineLayout layout;
@@ -471,8 +465,6 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
    cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
                                                          VK_ACCESS_2_SHADER_READ_BIT, 0, image, subresourceRange);
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); l++) {
@@ -561,8 +553,6 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
    /* Mark this image as actually being decompressed. */
    radv_update_dcc_metadata(cmd_buffer, image, subresourceRange, false);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
                                    radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
                                                          VK_ACCESS_2_SHADER_WRITE_BIT, 0, image, subresourceRange);
diff --git a/src/amd/vulkan/meta/radv_meta_fmask_expand.c b/src/amd/vulkan/meta/radv_meta_fmask_expand.c
index 34784e8dd40..a9326e4b878 100644
--- a/src/amd/vulkan/meta/radv_meta_fmask_expand.c
+++ b/src/amd/vulkan/meta/radv_meta_fmask_expand.c
@@ -96,7 +96,6 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
                          const VkImageSubresourceRange *subresourceRange)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    const uint32_t samples = image->vk.samples;
    const uint32_t samples_log2 = ffs(samples) - 1;
    unsigned layer_count = vk_image_subresource_layer_count(&image->vk, subresourceRange);
@@ -113,8 +112,6 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
       return;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_DESCRIPTORS);
-
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
    const VkImageViewUsageCreateInfo view_usage_info = {
@@ -167,8 +164,6 @@ radv_process_color_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *
 
    radv_image_view_finish(&iview);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    cmd_buffer->state.flush_bits |=
       RADV_CMD_FLAG_CS_PARTIAL_FLUSH | radv_src_access_flush(cmd_buffer, VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT,
                                                              VK_ACCESS_2_SHADER_WRITE_BIT, 0, image, &range);
diff --git a/src/amd/vulkan/meta/radv_meta_resolve.c b/src/amd/vulkan/meta/radv_meta_resolve.c
index e2e5d8fd7ca..c83af71f4ab 100644
--- a/src/amd/vulkan/meta/radv_meta_resolve.c
+++ b/src/amd/vulkan/meta/radv_meta_resolve.c
@@ -233,9 +233,6 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
                                  VkImageLayout dst_image_layout, const VkImageResolve2 *region)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
-
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE);
 
    assert(src_image->vk.samples > 1);
    assert(dst_image->vk.samples == 1);
@@ -376,8 +373,6 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
 
    radv_image_view_finish(&src_iview);
    radv_image_view_finish(&dst_iview);
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 /**
@@ -516,6 +511,8 @@ radv_CmdResolveImage2(VkCommandBuffer commandBuffer, const VkResolveImageInfo2 *
 
    radv_suspend_conditional_rendering(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    /* we can use the hw resolve only for single full resolves */
    if (pResolveImageInfo->regionCount == 1) {
       if (pResolveImageInfo->pRegions[0].srcOffset.x || pResolveImageInfo->pRegions[0].srcOffset.y ||
@@ -542,6 +539,8 @@ radv_CmdResolveImage2(VkCommandBuffer commandBuffer, const VkResolveImageInfo2 *
                     resolve_method);
    }
 
+   radv_meta_end(cmd_buffer);
+
    radv_resume_conditional_rendering(cmd_buffer);
 }
 
@@ -573,6 +572,8 @@ radv_cmd_buffer_resolve_rendering(struct radv_cmd_buffer *cmd_buffer, const VkRe
 
    radv_describe_begin_render_pass_resolve(cmd_buffer);
 
+   radv_meta_begin(cmd_buffer);
+
    /* Resolves happen before the end-of-subpass barriers get executed, so we have to make the
     * attachment shader-readable.
     */
@@ -786,5 +787,7 @@ radv_cmd_buffer_resolve_rendering(struct radv_cmd_buffer *cmd_buffer, const VkRe
       }
    }
 
+   radv_meta_end(cmd_buffer);
+
    radv_describe_end_render_pass_resolve(cmd_buffer);
 }
diff --git a/src/amd/vulkan/meta/radv_meta_resolve_cs.c b/src/amd/vulkan/meta/radv_meta_resolve_cs.c
index 64d6cf1d47c..476b7de9ae0 100644
--- a/src/amd/vulkan/meta/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/meta/radv_meta_resolve_cs.c
@@ -307,14 +307,10 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_
                                 VkImageLayout dst_image_layout, const VkImageResolve2 *region)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
 
    radv_fixup_resolve_dst_metadata(cmd_buffer, dst_image, dst_image_layout, &region->dstSubresource, &region->dstOffset,
                                    &region->extent, true);
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
-
    assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
    assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
    assert(vk_image_subresource_layer_count(&src_image->vk, &region->srcSubresource) ==
@@ -386,8 +382,6 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_
    radv_image_view_finish(&src_iview);
    radv_image_view_finish(&dst_iview);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    radv_fixup_resolve_dst_metadata(cmd_buffer, dst_image, dst_image_layout, &region->dstSubresource, &region->dstOffset,
                                    &region->extent, false);
 }
@@ -399,7 +393,6 @@ radv_meta_resolve_depth_stencil_cs(struct radv_cmd_buffer *cmd_buffer, struct ra
                                    VkResolveModeFlagBits resolve_mode, const VkImageResolve2 *region)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    VkPipelineLayout layout;
    VkPipeline pipeline;
    VkResult result;
@@ -414,9 +407,6 @@ radv_meta_resolve_depth_stencil_cs(struct radv_cmd_buffer *cmd_buffer, struct ra
    radv_fixup_resolve_dst_metadata(cmd_buffer, dst_image, dst_image_layout, &region->dstSubresource, &region->dstOffset,
                                    &region->extent, true);
 
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_CONSTANTS);
-
    const VkImageViewUsageCreateInfo src_iview_usage_info = {
       .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_USAGE_CREATE_INFO,
       .usage = VK_IMAGE_USAGE_SAMPLED_BIT,
@@ -506,8 +496,6 @@ radv_meta_resolve_depth_stencil_cs(struct radv_cmd_buffer *cmd_buffer, struct ra
    radv_image_view_finish(&src_iview);
    radv_image_view_finish(&dst_iview);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
-
    radv_fixup_resolve_dst_metadata(cmd_buffer, dst_image, dst_image_layout, &region->dstSubresource, &region->dstOffset,
                                    &region->extent, false);
 }
diff --git a/src/amd/vulkan/meta/radv_meta_resolve_fs.c b/src/amd/vulkan/meta/radv_meta_resolve_fs.c
index 7eeb9c6ea13..a6b5518b59f 100644
--- a/src/amd/vulkan/meta/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/meta/radv_meta_resolve_fs.c
@@ -376,10 +376,6 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv
                                  VkImageLayout dst_image_layout, const VkImageResolve2 *region)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
-
-   radv_meta_save(&saved_state, cmd_buffer,
-                  RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
 
    assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
    assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
@@ -479,8 +475,6 @@ radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv
 
    radv_image_view_finish(&src_iview);
    radv_image_view_finish(&dst_iview);
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
 
 void
@@ -491,7 +485,6 @@ radv_meta_resolve_depth_stencil_fs(struct radv_cmd_buffer *cmd_buffer, struct ra
                                    uint32_t view_mask)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    VkPipelineLayout layout;
    VkPipeline pipeline;
    VkResult result;
@@ -503,8 +496,6 @@ radv_meta_resolve_depth_stencil_fs(struct radv_cmd_buffer *cmd_buffer, struct ra
       return;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_GRAPHICS_PIPELINE | RADV_META_SAVE_DESCRIPTORS);
-
    const VkImageViewUsageCreateInfo src_iview_usage_info = {
       .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_USAGE_CREATE_INFO,
       .usage = VK_IMAGE_USAGE_SAMPLED_BIT,
@@ -609,6 +600,4 @@ radv_meta_resolve_depth_stencil_fs(struct radv_cmd_buffer *cmd_buffer, struct ra
 
    radv_image_view_finish(&src_iview);
    radv_image_view_finish(&dst_iview);
-
-   radv_meta_restore(&saved_state, cmd_buffer);
 }
diff --git a/src/amd/vulkan/radv_acceleration_structure.c b/src/amd/vulkan/radv_acceleration_structure.c
index 33586dc2b59..3afba3c2493 100644
--- a/src/amd/vulkan/radv_acceleration_structure.c
+++ b/src/amd/vulkan/radv_acceleration_structure.c
@@ -1021,7 +1021,6 @@ radv_CmdBuildAccelerationStructuresKHR(VkCommandBuffer commandBuffer, uint32_t i
 {
    VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
 
    VkResult result = radv_device_init_accel_struct_build_state(device);
    if (result != VK_SUCCESS) {
@@ -1029,14 +1028,15 @@ radv_CmdBuildAccelerationStructuresKHR(VkCommandBuffer commandBuffer, uint32_t i
       return;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
 
    cmd_buffer->state.current_event_type = EventInternalUnknown;
 
    vk_cmd_build_acceleration_structures(commandBuffer, &device->vk, &device->meta_state.device, infoCount, pInfos,
                                         ppBuildRangeInfos, &device->meta_state.accel_struct_build.build_args);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
 }
 
 VKAPI_ATTR void VKAPI_CALL
@@ -1045,9 +1045,9 @@ radv_CmdCopyAccelerationStructureKHR(VkCommandBuffer commandBuffer, const VkCopy
    VK_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
    VK_FROM_HANDLE(vk_acceleration_structure, src, pInfo->src);
    VK_FROM_HANDLE(vk_acceleration_structure, dst, pInfo->dst);
-   struct radv_meta_saved_state saved_state;
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
 
    radv_bvh_build_bind_pipeline(commandBuffer, RADV_META_OBJECT_KEY_BVH_COPY, copy_spv, sizeof(copy_spv),
                                 sizeof(struct copy_args), radv_build_flags(commandBuffer, 0) & RADV_BUILD_FLAG_BVH8);
@@ -1065,7 +1065,7 @@ radv_CmdCopyAccelerationStructureKHR(VkCommandBuffer commandBuffer, const VkCopy
    radv_CmdDispatchIndirect(commandBuffer, vk_buffer_to_handle(src->buffer),
                             src->offset + offsetof(struct radv_accel_struct_header, copy_dispatch_size));
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
 }
 
 VKAPI_ATTR void VKAPI_CALL
@@ -1089,9 +1089,9 @@ radv_CmdCopyMemoryToAccelerationStructureKHR(VkCommandBuffer commandBuffer,
    VK_FROM_HANDLE(vk_acceleration_structure, dst, pInfo->dst);
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radv_physical_device *pdev = radv_device_physical(device);
-   struct radv_meta_saved_state saved_state;
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
 
    radv_bvh_build_bind_pipeline(commandBuffer, RADV_META_OBJECT_KEY_BVH_COPY, copy_spv, sizeof(copy_spv),
                                 sizeof(struct copy_args), radv_build_flags(commandBuffer, 0) & RADV_BUILD_FLAG_BVH8);
@@ -1116,7 +1116,7 @@ radv_CmdCopyMemoryToAccelerationStructureKHR(VkCommandBuffer commandBuffer,
       radv_CmdDispatchBase(commandBuffer, 0, 0, 0, 256, 1, 1);
    }
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
 }
 
 VKAPI_ATTR void VKAPI_CALL
@@ -1127,9 +1127,9 @@ radv_CmdCopyAccelerationStructureToMemoryKHR(VkCommandBuffer commandBuffer,
    VK_FROM_HANDLE(vk_acceleration_structure, src, pInfo->src);
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radv_physical_device *pdev = radv_device_physical(device);
-   struct radv_meta_saved_state saved_state;
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
+   radv_meta_save(cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
 
    radv_bvh_build_bind_pipeline(commandBuffer, RADV_META_OBJECT_KEY_BVH_COPY, copy_spv, sizeof(copy_spv),
                                 sizeof(struct copy_args), radv_build_flags(commandBuffer, 0) & RADV_BUILD_FLAG_BVH8);
@@ -1158,7 +1158,7 @@ radv_CmdCopyAccelerationStructureToMemoryKHR(VkCommandBuffer commandBuffer,
       radv_CmdDispatchBase(commandBuffer, 0, 0, 0, 256, 1, 1);
    }
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
 
    /* Set the header of the serialized data. */
    uint8_t header_data[2 * VK_UUID_SIZE];
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index e0b7e66f37d..6be6069734f 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -26,7 +26,6 @@
 #include "radv_sdma.h"
 #include "radv_shader.h"
 #include "radv_shader_object.h"
-#include "radv_sqtt.h"
 #include "sid.h"
 #include "vk_command_pool.h"
 #include "vk_enum_defines.h"
@@ -9864,6 +9863,11 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
     */
    if (cmd_buffer->vk.render_pass)
       radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);
+
+   bool inside_meta_op = cmd_buffer->state.meta.inside_meta_op;
+   if (!inside_meta_op)
+      radv_meta_begin(cmd_buffer);
+
    uint32_t color_samples = 0, ds_samples = 0;
    struct radv_attachment color_att[MAX_RTS];
    for (uint32_t i = 0; i < pRenderingInfo->colorAttachmentCount; i++) {
@@ -9994,8 +9998,6 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
                                           sample_locs_info);
       }
    }
-   if (cmd_buffer->vk.render_pass)
-      radv_describe_barrier_end(cmd_buffer);
 
    const VkRenderingFragmentShadingRateAttachmentInfoKHR *fsr_info =
       vk_find_struct_const(pRenderingInfo->pNext, RENDERING_FRAGMENT_SHADING_RATE_ATTACHMENT_INFO_KHR);
@@ -10011,6 +10013,54 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
       vrs_texel_size = fsr_info->shadingRateAttachmentTexelSize;
    }
 
+   if (vrs_att.iview && pdev->info.gfx_level == GFX10_3) {
+      VkRect2D render_area = pRenderingInfo->renderArea;
+      if (ds_att.iview && radv_htile_enabled(ds_att.iview->image, ds_att.iview->vk.base_mip_level)) {
+         /* When we have a VRS attachment and a depth/stencil attachment, we just need to copy the
+          * VRS rates to the HTILE buffer of the attachment.
+          */
+         struct radv_image_view *ds_iview = ds_att.iview;
+         struct radv_image *ds_image = ds_iview->image;
+         uint32_t level = ds_iview->vk.base_mip_level;
+
+         /* HTILE buffer */
+         uint64_t htile_offset =
+            ds_image->planes[0].surface.meta_offset + ds_image->planes[0].surface.u.gfx9.meta_levels[level].offset;
+         const uint64_t htile_va = ds_image->bindings[0].addr + htile_offset;
+
+         assert(render_area.offset.x + render_area.extent.width <= ds_image->vk.extent.width &&
+                render_area.offset.x + render_area.extent.height <= ds_image->vk.extent.height);
+
+         /* Copy the VRS rates to the HTILE buffer. */
+         radv_copy_vrs_htile(cmd_buffer, vrs_att.iview, &render_area, ds_image, htile_va, true);
+      } else {
+         /* When a subpass uses a VRS attachment without binding a depth/stencil attachment, or when
+          * HTILE isn't enabled, we use a fallback that copies the VRS rates to our internal HTILE buffer.
+          */
+         struct radv_image *ds_image = radv_cmd_buffer_get_vrs_image(cmd_buffer);
+
+         if (ds_image && render_area.offset.x < ds_image->vk.extent.width &&
+             render_area.offset.y < ds_image->vk.extent.height) {
+            /* HTILE buffer */
+            struct radv_buffer *htile_buffer = device->vrs.buffer;
+            const uint64_t htile_va = htile_buffer->vk.device_address;
+
+            render_area.extent.width = MIN2(render_area.extent.width, ds_image->vk.extent.width - render_area.offset.x);
+            render_area.extent.height =
+               MIN2(render_area.extent.height, ds_image->vk.extent.height - render_area.offset.y);
+
+            /* Copy the VRS rates to the HTILE buffer. */
+            radv_copy_vrs_htile(cmd_buffer, vrs_att.iview, &render_area, ds_image, htile_va, false);
+         }
+      }
+   }
+
+   if (!inside_meta_op)
+      radv_meta_end(cmd_buffer);
+
+   if (cmd_buffer->vk.render_pass)
+      radv_describe_barrier_end(cmd_buffer);
+
    /* Now that we've done any layout transitions which may invoke meta, we can
     * fill out the actual rendering info and set up for the client's render pass.
     */
@@ -10046,48 +10096,6 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
    if (pdev->info.gfx_level >= GFX12)
       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_GFX12_HIZ_WA_STATE;
 
-   if (render->vrs_att.iview && pdev->info.gfx_level == GFX10_3) {
-      if (render->ds_att.iview &&
-          radv_htile_enabled(render->ds_att.iview->image, render->ds_att.iview->vk.base_mip_level)) {
-         /* When we have a VRS attachment and a depth/stencil attachment, we just need to copy the
-          * VRS rates to the HTILE buffer of the attachment.
-          */
-         struct radv_image_view *ds_iview = render->ds_att.iview;
-         struct radv_image *ds_image = ds_iview->image;
-         uint32_t level = ds_iview->vk.base_mip_level;
-
-         /* HTILE buffer */
-         uint64_t htile_offset =
-            ds_image->planes[0].surface.meta_offset + ds_image->planes[0].surface.u.gfx9.meta_levels[level].offset;
-         const uint64_t htile_va = ds_image->bindings[0].addr + htile_offset;
-
-         assert(render->area.offset.x + render->area.extent.width <= ds_image->vk.extent.width &&
-                render->area.offset.x + render->area.extent.height <= ds_image->vk.extent.height);
-
-         /* Copy the VRS rates to the HTILE buffer. */
-         radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview, &render->area, ds_image, htile_va, true);
-      } else {
-         /* When a subpass uses a VRS attachment without binding a depth/stencil attachment, or when
-          * HTILE isn't enabled, we use a fallback that copies the VRS rates to our internal HTILE buffer.
-          */
-         struct radv_image *ds_image = radv_cmd_buffer_get_vrs_image(cmd_buffer);
-
-         if (ds_image && render->area.offset.x < ds_image->vk.extent.width &&
-             render->area.offset.y < ds_image->vk.extent.height) {
-            /* HTILE buffer */
-            struct radv_buffer *htile_buffer = device->vrs.buffer;
-            const uint64_t htile_va = htile_buffer->vk.device_address;
-
-            VkRect2D area = render->area;
-            area.extent.width = MIN2(area.extent.width, ds_image->vk.extent.width - area.offset.x);
-            area.extent.height = MIN2(area.extent.height, ds_image->vk.extent.height - area.offset.y);
-
-            /* Copy the VRS rates to the HTILE buffer. */
-            radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview, &area, ds_image, htile_va, false);
-         }
-      }
-   }
-
    const uint32_t minx = render->area.offset.x;
    const uint32_t miny = render->area.offset.y;
    const uint32_t maxx = minx + render->area.extent.width;
@@ -14706,6 +14714,10 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, uint32_t dep_count, const VkDep
 
    radv_gang_barrier(cmd_buffer, src_stage_mask, 0);
 
+   bool inside_meta_op = cmd_buffer->state.meta.inside_meta_op;
+   if (!inside_meta_op)
+      radv_meta_begin(cmd_buffer);
+
    for (uint32_t dep_idx = 0; dep_idx < dep_count; dep_idx++) {
       const VkDependencyInfo *dep_info = &dep_infos[dep_idx];
 
@@ -14739,6 +14751,9 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, uint32_t dep_count, const VkDep
       }
    }
 
+   if (!inside_meta_op)
+      radv_meta_end(cmd_buffer);
+
    radv_gang_barrier(cmd_buffer, 0, dst_stage_mask);
 
    if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) {
diff --git a/src/amd/vulkan/radv_cmd_buffer.h b/src/amd/vulkan/radv_cmd_buffer.h
index 66e5966f1d8..1aaf306e84d 100644
--- a/src/amd/vulkan/radv_cmd_buffer.h
+++ b/src/amd/vulkan/radv_cmd_buffer.h
@@ -284,6 +284,36 @@ enum radv_depth_clamp_mode {
    RADV_DEPTH_CLAMP_MODE_DISABLED = 3,     /* Disable depth clamping */
 };
 
+struct radv_meta_saved_descriptor_state {
+   struct radv_descriptor_set *old_descriptor_set0;
+   bool old_descriptor_set0_valid;
+   uint64_t old_descriptor_buffer0;
+};
+
+struct radv_meta_saved_state {
+   uint32_t flags;
+
+   struct radv_meta_saved_descriptor_state graphics_descriptors;
+   struct radv_meta_saved_descriptor_state compute_descriptors;
+
+   uint64_t old_descriptor_buffer_addr0;
+
+   struct radv_graphics_pipeline *old_graphics_pipeline;
+   struct radv_compute_pipeline *old_compute_pipeline;
+   struct radv_dynamic_state dynamic;
+
+   struct radv_shader_object *old_shader_objs[MESA_VULKAN_SHADER_STAGES];
+
+   char push_constants[MAX_PUSH_CONSTANTS_SIZE];
+
+   unsigned active_emulated_pipeline_queries;
+   unsigned active_emulated_prims_gen_queries;
+   unsigned active_emulated_prims_xfb_queries;
+   unsigned active_occlusion_queries;
+
+   bool inside_meta_op;
+};
+
 struct radv_cmd_state {
    /* Vertex descriptors */
    uint64_t vb_va;
@@ -314,6 +344,8 @@ struct radv_cmd_state {
 
    struct radv_rendering_state render;
 
+   struct radv_meta_saved_state meta;
+
    /* Index buffer */
    uint32_t index_type;
    uint32_t max_index_count;
diff --git a/src/amd/vulkan/radv_dgc.c b/src/amd/vulkan/radv_dgc.c
index d2e8a28c008..eb22a5f870f 100644
--- a/src/amd/vulkan/radv_dgc.c
+++ b/src/amd/vulkan/radv_dgc.c
@@ -3232,7 +3232,6 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
    const struct radv_physical_device *pdev = radv_device_physical(device);
    struct radv_dgc_pc_layout_info dgc_pc_info;
-   struct radv_meta_saved_state saved_state;
    unsigned upload_offset, upload_size = 0;
    void *upload_data;
 
@@ -3317,7 +3316,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
       upload_data = (char *)upload_data + dgc_pc_info.size;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
 
    radv_meta_bind_compute_pipeline(cmd_buffer, layout->pipeline);
 
@@ -3327,7 +3326,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
    unsigned block_count = MAX2(1, DIV_ROUND_UP(pGeneratedCommandsInfo->maxSequenceCount, 64));
    radv_CmdDispatchBase(radv_cmd_buffer_to_handle(cmd_buffer), 0, 0, 0, block_count, 1, 1);
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
 }
 
 static void
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 4bd12ba31b7..3a459b6fc29 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1792,7 +1792,6 @@ radv_query_shader(struct radv_cmd_buffer *cmd_buffer, VkQueryType query_type, st
                   uint32_t flags, uint32_t pipeline_stats_mask, uint32_t avail_offset, bool uses_emulated_queries)
 {
    struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
-   struct radv_meta_saved_state saved_state;
    VkPipelineLayout layout;
    VkPipeline pipeline;
    VkResult result;
@@ -1803,7 +1802,7 @@ radv_query_shader(struct radv_cmd_buffer *cmd_buffer, VkQueryType query_type, st
       return;
    }
 
-   radv_meta_save(&saved_state, cmd_buffer, RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS);
+   radv_meta_begin(cmd_buffer);
 
    radv_meta_bind_compute_pipeline(cmd_buffer, pipeline);
 
@@ -1837,7 +1836,7 @@ radv_query_shader(struct radv_cmd_buffer *cmd_buffer, VkQueryType query_type, st
    cmd_buffer->active_query_flush_bits |=
       RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE;
 
-   radv_meta_restore(&saved_state, cmd_buffer);
+   radv_meta_end(cmd_buffer);
 }
 
 static uint32_t
@@ -2539,6 +2538,8 @@ radv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uin
     */
    cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;
 
+   radv_meta_begin(cmd_buffer);
+
    flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo, radv_buffer_get_va(pool->bo) + firstQuery * pool->stride,
                                   queryCount * pool->stride, value);
 
@@ -2549,6 +2550,8 @@ radv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uin
                           radv_buffer_get_va(pool->bo) + pool->availability_offset + firstQuery * 4, queryCount * 4, 0);
    }
 
+   radv_meta_end(cmd_buffer);
+
    if (flush_bits) {
       /* Only need to flush caches for the compute shader path. */
       cmd_buffer->pending_reset_query = true;