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intel/genxml: Fix SLICE_HASH_TABLE struct on XeHP.

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It's now an array with 7 tables, each table is intended to specify the
pixel pipe hashing behavior for every possible slice count between 2
and 8, however that doesn't actually work, among other reasons due to
hardware bugs that will cause the GPU to erroneously access the table
at the wrong index in some cases, so in practice all 7 tables need to
be initialized to the same value.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13569>
This commit is contained in:
Francisco Jerez 2021-07-21 14:30:28 -07:00
parent a748b264e8
commit ae5fa3f518
1 changed files with 6 additions and 4 deletions
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10
src/intel/genxml/gen125.xml
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@ -1201,10 +1201,12 @@
<field name="Component Override W" start="15" end="15" type="bool"/>
</struct>
<struct name="SLICE_HASH_TABLE" length="32">
<group count="16" start="0" size="64">
<group count="16" start="0" size="4">
<field name="Entry" start="0" end="3" type="uint"/>
<struct name="SLICE_HASH_TABLE" length="224">
<group count="7" start="0" size="1024">
<group count="16" start="0" size="64">
<group count="16" start="0" size="4">
<field name="Entry" start="0" end="3" type="uint"/>
</group>
</group>
</group>
</struct>