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tu: Drop HIC support for depth images

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This becomes more complex for gen8, as the lrz-status is per-slice.
Additionally the lrz-status layout isn't "stable" between GPUs of a
given generation.. the hw can change the layout, as it's not really
considered a sw interface.

Dropping HIC support for depth images removes one of two places in
the driver that reach into the lrz-status memory.  The other is
tu_trace_end_render_pass(), but that is relatively safer.. at the
point that it is reading the status, all slices should be in the
same state.

Since HIC is not required for depth images, lets just delete some
code and not have this problem.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39375>
This commit is contained in:
Rob Clark 2026-01-23 07:02:22 -08:00 • committed by Marge Bot
parent 602c356c58
commit ae3d900e37
4 changed files with 8 additions and 59 deletions
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12
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -2676,15 +2676,13 @@ tu_CopyMemoryToImageEXT(VkDevice _device,
VK_FROM_HANDLE(tu_device, device, _device);
VK_FROM_HANDLE(tu_image, dst_image, info->dstImage);
assert(!dst_image->lrz_layout.lrz_total_size);
for (unsigned i = 0; i < info->regionCount; i++) {
tu_copy_memory_to_image(device, dst_image, &info->pRegions[i],
info->flags & VK_HOST_IMAGE_COPY_MEMCPY_EXT);
}
if (dst_image->lrz_layout.lrz_total_size) {
TU_CALLX(device, tu_disable_lrz_cpu)(device, dst_image);
}
return VK_SUCCESS;
}
@ -3328,6 +3326,8 @@ tu_CopyImageToImageEXT(VkDevice _device,
bool copy_memcpy = pCopyImageToImageInfo->flags &
VK_HOST_IMAGE_COPY_MEMCPY_EXT;
assert(!dst_image->lrz_layout.lrz_total_size);
for (uint32_t i = 0; i < pCopyImageToImageInfo->regionCount; ++i) {
if (src_image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
VkImageCopy2 info = pCopyImageToImageInfo->pRegions[i];
@ -3345,10 +3345,6 @@ tu_CopyImageToImageEXT(VkDevice _device,
copy_memcpy);
}
if (dst_image->lrz_layout.lrz_total_size) {
TU_CALLX(device, tu_disable_lrz_cpu)(device, dst_image);
}
return VK_SUCCESS;
}

7
src/freedreno/vulkan/tu_formats.cc
View file

@ -160,10 +160,11 @@ tu_physical_device_get_format_properties(
if (supported_tex)
buffer |= VK_FORMAT_FEATURE_2_UNIFORM_TEXEL_BUFFER_BIT;
/* We don't support D24S8 because copying just one aspect would require a
* special codepath and that doesn't seem worth it.
/* We don't support depth formats, as HIC would require disabling LRZ on
* the CPU. Additionally, D24S8 would require a special codepath for copying
* a single aspect, and that doesn't seem worth it.
*/
if (!is_npot && vk_format != VK_FORMAT_D24_UNORM_S8_UINT) {
if (!is_npot && !util_format_has_depth(util_format_description(format))) {
optimal |= VK_FORMAT_FEATURE_2_HOST_IMAGE_TRANSFER_BIT_EXT;
}

44
src/freedreno/vulkan/tu_lrz.cc
View file

@ -925,50 +925,6 @@ tu_disable_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
}
TU_GENX(tu_disable_lrz);
/* Disable LRZ from the CPU, for host image copy */
template <chip CHIP>
void
tu_disable_lrz_cpu(struct tu_device *device, struct tu_image *image)
{
if (!device->physical_device->info->props.has_lrz_dir_tracking)
return;
if (!image->lrz_layout.lrz_total_size)
return;
const unsigned lrz_dir_offset = offsetof(fd_lrzfc_layout<CHIP>,
buffer[0].dir_track);
uint8_t *lrz_dir_tracking =
(uint8_t *)image->map + image->lrz_layout.lrz_fc_offset + lrz_dir_offset;
*lrz_dir_tracking = FD_LRZ_GPU_DIR_DISABLED;
if (image->mem->bo->cached_non_coherent) {
tu_bo_sync_cache(
device, image->mem->bo,
image->mem_offset + image->lrz_layout.lrz_offset + lrz_dir_offset, 1,
TU_MEM_SYNC_CACHE_TO_GPU);
}
if (CHIP >= A7XX) {
const unsigned lrz_dir_offset2 = offsetof(fd_lrzfc_layout<CHIP>,
buffer[1].dir_track);
uint8_t *lrz_dir_tracking2 =
(uint8_t *)image->map + image->lrz_layout.lrz_fc_offset + lrz_dir_offset2;
*lrz_dir_tracking2 = FD_LRZ_GPU_DIR_DISABLED;
if (image->mem->bo->cached_non_coherent) {
tu_bo_sync_cache(
device, image->mem->bo,
image->mem_offset + image->lrz_layout.lrz_offset + lrz_dir_offset2, 1,
TU_MEM_SYNC_CACHE_TO_GPU);
}
}
}
TU_GENX(tu_disable_lrz_cpu);
/* Clear LRZ, used for out of renderpass depth clears. */
template <chip CHIP>
void

4
src/freedreno/vulkan/tu_lrz.h
View file

@ -65,10 +65,6 @@ void
tu_disable_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
struct tu_image *image);
template <chip CHIP>
void
tu_disable_lrz_cpu(struct tu_device *device, struct tu_image *image);
template <chip CHIP>
void
tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,