fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 11:28:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

intel: Disable 16x MSAA support on Xe3

Browse source 
16x MSAA isn't supported at all on certain Xe3 variants, and on its way
out on the rest.  Most vendors choose not to support it, and many apps
offer more modern multisampling and upscaling techniques these days.

Only 2/4/8x are supported going forward.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36592>
(cherry picked from commit dc2c3cf06b)
This commit is contained in:
Kenneth Graunke 2025-06-11 21:37:08 -07:00 • committed by Eric Engestrom
parent e561070e1a
commit adf2da3ef2
5 changed files with 6 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -6414,7 +6414,7 @@
"description": "intel: Disable 16x MSAA support on Xe3",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

2
src/gallium/drivers/iris/iris_formats.c
View file

@ -112,7 +112,7 @@ iris_is_format_supported(struct pipe_screen *pscreen,
{
struct iris_screen *screen = (struct iris_screen *) pscreen;
const struct intel_device_info *devinfo = screen->devinfo;
uint32_t max_samples = devinfo->ver == 8 ? 8 : 16;
uint32_t max_samples = devinfo->ver == 8 || devinfo->ver >= 30 ? 8 : 16;
if (sample_count > max_samples ||
!util_is_power_of_two_or_zero(sample_count))

3
src/gallium/drivers/iris/iris_state.c
View file

@ -3796,7 +3796,8 @@ iris_set_framebuffer_state(struct pipe_context *ctx,
ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE;
/* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */
if (GFX_VER >= 9 && (cso->samples == 16 || samples == 16))
if (GFX_VER >= 9 && GFX_VER < 30 &&
(cso->samples == 16 || samples == 16))
ice->state.stage_dirty |= IRIS_STAGE_DIRTY_FS;
/* We may need to emit blend state for Wa_14018912822. */

2
src/intel/isl/isl.c
View file

@ -511,7 +511,7 @@ isl_device_get_supported_tilings(const struct isl_device *dev)
isl_sample_count_mask_t ATTRIBUTE_CONST
isl_device_get_sample_counts(const struct isl_device *dev)
{
if (ISL_GFX_VER(dev) >= 9) {
if (ISL_GFX_VER(dev) >= 9 && ISL_GFX_VER(dev) < 30) {
return ISL_SAMPLE_COUNT_1_BIT |
ISL_SAMPLE_COUNT_2_BIT |
ISL_SAMPLE_COUNT_4_BIT |

1
src/intel/vulkan/anv_physical_device.c
View file

@ -478,6 +478,7 @@ get_features(const struct anv_physical_device *pdevice,
.sparseResidency8Samples = has_sparse_or_fake &&
pdevice->info.verx10 != 125,
.sparseResidency16Samples = has_sparse_or_fake &&
pdevice->info.ver < 30 &&
pdevice->info.verx10 != 125,
.variableMultisampleRate = true,
.inheritedQueries = true,