From adde1dbae5d1bb9f804dbbb9ba57351b33f113d2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Sun, 24 Mar 2024 18:13:04 -0400
Subject: [PATCH] radeonsi/gfx11: enable DCC fast clears for 8-bit and 16-bit
 formats

They seem to work fine.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
---
 src/gallium/drivers/radeonsi/si_clear.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 8873c2cb543..a7349ef8882 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -291,10 +291,6 @@ static bool gfx11_get_dcc_clear_parameters(struct si_screen *sscreen, enum pipe_
    unsigned start_bit = UINT_MAX;
    unsigned end_bit = 0;
 
-   /* TODO: 8bpp and 16bpp fast DCC clears don't work. */
-   if (desc->block.bits <= 16)
-      return false;
-
    /* Find the used bit range. */
    for (unsigned i = 0; i < 4; i++) {
       unsigned swizzle = desc->swizzle[i];