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intel/brw: Remove Gfx8- code from inst FC and F macros
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
ccece38623
commit
add6ea8a22
1 changed files with 161 additions and 162 deletions
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@ -54,7 +54,7 @@ static inline void brw_inst_set_bits(brw_inst *inst,
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unsigned high, unsigned low,
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uint64_t value);
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#define FC(name, hi4, lo4, hi12, lo12, assertions) \
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#define FC(name, hi9, lo9, hi12, lo12, assertions) \
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static inline void \
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brw_inst_set_##name(const struct intel_device_info *devinfo, \
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brw_inst *inst, uint64_t v) \
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@ -63,7 +63,7 @@ brw_inst_set_##name(const struct intel_device_info *devinfo, \
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if (devinfo->ver >= 12) \
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brw_inst_set_bits(inst, hi12, lo12, v); \
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else \
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brw_inst_set_bits(inst, hi4, lo4, v); \
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brw_inst_set_bits(inst, hi9, lo9, v); \
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} \
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static inline uint64_t \
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brw_inst_##name(const struct intel_device_info *devinfo, \
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@ -73,13 +73,13 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
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if (devinfo->ver >= 12) \
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return brw_inst_bits(inst, hi12, lo12); \
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else \
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return brw_inst_bits(inst, hi4, lo4); \
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return brw_inst_bits(inst, hi9, lo9); \
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}
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/* A simple macro for fields which stay in the same place on all generations,
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* except for Gfx12!
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*/
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#define F(name, hi4, lo4, hi12, lo12) FC(name, hi4, lo4, hi12, lo12, true)
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#define F(name, hi9, lo9, hi12, lo12) FC(name, hi9, lo9, hi12, lo12, true)
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/* A simple macro for fields which stay in the same place on all generations,
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* except for Gfx12 and Gfx20.
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@ -327,50 +327,50 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
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}
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FV20(src1_vstride, /* 4+ */ 120, 117, /* 12+ */ 119, 116, /* 20+ */ 118, 116)
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F(src1_width, /* 4+ */ 116, 114, /* 12+ */ 115, 113)
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F(src1_da16_swiz_w, /* 4+ */ 115, 114, /* 12+ */ -1, -1)
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F(src1_da16_swiz_z, /* 4+ */ 113, 112, /* 12+ */ -1, -1)
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F(src1_hstride, /* 4+ */ 113, 112, /* 12+ */ 97, 96)
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F(src1_address_mode, /* 4+ */ 111, 111, /* 12+ */ 112, 112)
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F(src1_width, /* 9+ */ 116, 114, /* 12+ */ 115, 113)
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F(src1_da16_swiz_w, /* 9+ */ 115, 114, /* 12+ */ -1, -1)
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F(src1_da16_swiz_z, /* 9+ */ 113, 112, /* 12+ */ -1, -1)
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F(src1_hstride, /* 9+ */ 113, 112, /* 12+ */ 97, 96)
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F(src1_address_mode, /* 9+ */ 111, 111, /* 12+ */ 112, 112)
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/** Src1.SrcMod @{ */
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F(src1_negate, /* 4+ */ 110, 110, /* 12+ */ 121, 121)
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F(src1_abs, /* 4+ */ 109, 109, /* 12+ */ 120, 120)
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F(src1_negate, /* 9+ */ 110, 110, /* 12+ */ 121, 121)
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F(src1_abs, /* 9+ */ 109, 109, /* 12+ */ 120, 120)
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/** @} */
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F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ 111, 108)
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F(src1_da_reg_nr, /* 4+ */ 108, 101, /* 12+ */ 111, 104)
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F(src1_da16_subreg_nr, /* 4+ */ 100, 100, /* 12+ */ -1, -1)
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F(src1_da_reg_nr, /* 9+ */ 108, 101, /* 12+ */ 111, 104)
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F(src1_da16_subreg_nr, /* 9+ */ 100, 100, /* 12+ */ -1, -1)
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FD20(src1_da1_subreg_nr, /* 4+ */ 100, 96, /* 12+ */ 103, 99, /* 20+ */ 103, 99, -1)
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F(src1_da16_swiz_y, /* 4+ */ 99, 98, /* 12+ */ -1, -1)
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F(src1_da16_swiz_x, /* 4+ */ 97, 96, /* 12+ */ -1, -1)
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F(src1_da16_swiz_y, /* 9+ */ 99, 98, /* 12+ */ -1, -1)
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F(src1_da16_swiz_x, /* 9+ */ 97, 96, /* 12+ */ -1, -1)
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F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ 91, 88)
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FI(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89, /* 12+ */ 47, 98)
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F(src1_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
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F(src1_is_imm, /* 9+ */ -1, -1, /* 12+ */ 47, 47)
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FV20(src0_vstride, /* 4+ */ 88, 85, /* 12+ */ 87, 84, /* 20+ */ 86, 84)
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F(src0_width, /* 4+ */ 84, 82, /* 12+ */ 83, 81)
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F(src0_da16_swiz_w, /* 4+ */ 83, 82, /* 12+ */ -1, -1)
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F(src0_da16_swiz_z, /* 4+ */ 81, 80, /* 12+ */ -1, -1)
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F(src0_hstride, /* 4+ */ 81, 80, /* 12+ */ 65, 64)
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F(src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ 80, 80)
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F(src0_width, /* 9+ */ 84, 82, /* 12+ */ 83, 81)
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F(src0_da16_swiz_w, /* 9+ */ 83, 82, /* 12+ */ -1, -1)
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F(src0_da16_swiz_z, /* 9+ */ 81, 80, /* 12+ */ -1, -1)
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F(src0_hstride, /* 9+ */ 81, 80, /* 12+ */ 65, 64)
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F(src0_address_mode, /* 9+ */ 79, 79, /* 12+ */ 80, 80)
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/** Src0.SrcMod @{ */
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F(src0_negate, /* 4+ */ 78, 78, /* 12+ */ 45, 45)
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F(src0_abs, /* 4+ */ 77, 77, /* 12+ */ 44, 44)
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F(src0_negate, /* 9+ */ 78, 78, /* 12+ */ 45, 45)
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F(src0_abs, /* 9+ */ 77, 77, /* 12+ */ 44, 44)
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/** @} */
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F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ 79, 76)
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F(src0_da_reg_nr, /* 4+ */ 76, 69, /* 12+ */ 79, 72)
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F(src0_da16_subreg_nr, /* 4+ */ 68, 68, /* 12+ */ -1, -1)
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F(src0_da_reg_nr, /* 9+ */ 76, 69, /* 12+ */ 79, 72)
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F(src0_da16_subreg_nr, /* 9+ */ 68, 68, /* 12+ */ -1, -1)
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FD20(src0_da1_subreg_nr, /* 4+ */ 68, 64, /* 12+ */ 71, 67, /* 20+ */ 71, 67, 87)
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F(src0_da16_swiz_y, /* 4+ */ 67, 66, /* 12+ */ -1, -1)
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F(src0_da16_swiz_x, /* 4+ */ 65, 64, /* 12+ */ -1, -1)
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F(dst_address_mode, /* 4+ */ 63, 63, /* 12+ */ 35, 35)
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F(dst_hstride, /* 4+ */ 62, 61, /* 12+ */ 49, 48)
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F(src0_da16_swiz_y, /* 9+ */ 67, 66, /* 12+ */ -1, -1)
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F(src0_da16_swiz_x, /* 9+ */ 65, 64, /* 12+ */ -1, -1)
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F(dst_address_mode, /* 9+ */ 63, 63, /* 12+ */ 35, 35)
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F(dst_hstride, /* 9+ */ 62, 61, /* 12+ */ 49, 48)
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F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ 63, 60)
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F(dst_da_reg_nr, /* 4+ */ 60, 53, /* 12+ */ 63, 56)
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F(dst_da16_subreg_nr, /* 4+ */ 52, 52, /* 12+ */ -1, -1)
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F(dst_da_reg_nr, /* 9+ */ 60, 53, /* 12+ */ 63, 56)
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F(dst_da16_subreg_nr, /* 9+ */ 52, 52, /* 12+ */ -1, -1)
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FD20(dst_da1_subreg_nr, /* 4+ */ 52, 48, /* 12+ */ 55, 51, /* 20+ */ 55, 51, 33)
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F(da16_writemask, /* 4+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
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F(da16_writemask, /* 9+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
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F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ 43, 40)
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FI(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 46, 66)
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F(src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
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F(src0_is_imm, /* 9+ */ -1, -1, /* 12+ */ 46, 46)
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F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ 39, 36)
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F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ 50, 50)
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F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
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@ -385,18 +385,18 @@ FF(flag_subreg_nr,
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/* 8: */ 32, 32,
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/* 12: */ 22, 22,
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/* 20: */ 21, 21)
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F(saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
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F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
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F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
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F(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33)
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FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20)
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F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
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F(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
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F(saturate, /* 9+ */ 31, 31, /* 12+ */ 34, 34)
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F(debug_control, /* 9+ */ 30, 30, /* 12+ */ 30, 30)
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F(cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
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F(branch_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33)
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FC(acc_wr_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20)
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F(cond_modifier, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
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F(math_function, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
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F20(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16, /* 20+ */ 20, 18)
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F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
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F(pred_inv, /* 9+ */ 20, 20, /* 12+ */ 28, 28)
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F20(pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24, /* 20+ */ 27, 26)
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F(thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
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F(atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
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F(thread_control, /* 9+ */ 15, 14, /* 12+ */ -1, -1)
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F(atomic_control, /* 9+ */ -1, -1, /* 12+ */ 32, 32)
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F20(qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20, /* 20+ */ 25, 24)
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FF(nib_control,
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/* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
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@ -409,27 +409,27 @@ F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
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F20(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
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FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
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/* Bit 7 is Reserved (for future Opcode expansion) */
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F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
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F(hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
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/**
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* Three-source instructions:
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* @{
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*/
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F(3src_src2_reg_nr, /* 4+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */
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F(3src_a16_src2_subreg_nr, /* 4+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
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F(3src_a16_src2_swizzle, /* 4+ */ 114, 107, /* 12+ */ -1, -1)
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F(3src_a16_src2_rep_ctrl, /* 4+ */ 106, 106, /* 12+ */ -1, -1)
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F(3src_src1_reg_nr, /* 4+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */
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F(3src_a16_src1_subreg_nr, /* 4+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
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F(3src_a16_src1_swizzle, /* 4+ */ 93, 86, /* 12+ */ -1, -1)
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F(3src_a16_src1_rep_ctrl, /* 4+ */ 85, 85, /* 12+ */ -1, -1)
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F(3src_src0_reg_nr, /* 4+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */
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F(3src_a16_src0_subreg_nr, /* 4+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
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F(3src_a16_src0_swizzle, /* 4+ */ 72, 65, /* 12+ */ -1, -1)
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F(3src_a16_src0_rep_ctrl, /* 4+ */ 64, 64, /* 12+ */ -1, -1)
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F(3src_dst_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */
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F(3src_a16_dst_subreg_nr, /* 4+ */ 55, 53, /* 12+ */ -1, -1)
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F(3src_a16_dst_writemask, /* 4+ */ 52, 49, /* 12+ */ -1, -1)
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F(3src_src2_reg_nr, /* 9+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */
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F(3src_a16_src2_subreg_nr, /* 9+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
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F(3src_a16_src2_swizzle, /* 9+ */ 114, 107, /* 12+ */ -1, -1)
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F(3src_a16_src2_rep_ctrl, /* 9+ */ 106, 106, /* 12+ */ -1, -1)
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F(3src_src1_reg_nr, /* 9+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */
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F(3src_a16_src1_subreg_nr, /* 9+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
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F(3src_a16_src1_swizzle, /* 9+ */ 93, 86, /* 12+ */ -1, -1)
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F(3src_a16_src1_rep_ctrl, /* 9+ */ 85, 85, /* 12+ */ -1, -1)
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F(3src_src0_reg_nr, /* 9+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */
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F(3src_a16_src0_subreg_nr, /* 9+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
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F(3src_a16_src0_swizzle, /* 9+ */ 72, 65, /* 12+ */ -1, -1)
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F(3src_a16_src0_rep_ctrl, /* 9+ */ 64, 64, /* 12+ */ -1, -1)
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F(3src_dst_reg_nr, /* 9+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */
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F(3src_a16_dst_subreg_nr, /* 9+ */ 55, 53, /* 12+ */ -1, -1)
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F(3src_a16_dst_writemask, /* 9+ */ 52, 49, /* 12+ */ -1, -1)
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F8(3src_a16_nib_ctrl, /* 4+ */ 47, 47, /* 8+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
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F8(3src_a16_dst_hw_type, /* 4+ */ 45, 44, /* 8+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
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F8(3src_a16_src_hw_type, /* 4+ */ 43, 42, /* 8+ */ 45, 43, /* 12+ */ -1, -1)
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@ -443,24 +443,24 @@ F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, -
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F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1)
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F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1)
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F8(3src_a16_flag_subreg_nr, /* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1)
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F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34)
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F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30)
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F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
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FC(3src_acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20)
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F(3src_cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92)
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F(3src_exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16)
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F(3src_pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28)
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F(3src_saturate, /* 9+ */ 31, 31, /* 12+ */ 34, 34)
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F(3src_debug_control, /* 9+ */ 30, 30, /* 12+ */ 30, 30)
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F(3src_cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
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FC(3src_acc_wr_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20)
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F(3src_cond_modifier, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
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F(3src_exec_size, /* 9+ */ 23, 21, /* 12+ */ 18, 16)
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F(3src_pred_inv, /* 9+ */ 20, 20, /* 12+ */ 28, 28)
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F20(3src_pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24, /* 20+ */ 27, 26)
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F(3src_thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1)
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F(3src_atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32)
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F(3src_thread_control, /* 9+ */ 15, 14, /* 12+ */ -1, -1)
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F(3src_atomic_control, /* 9+ */ -1, -1, /* 12+ */ 32, 32)
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F20(3src_qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20, /* 20+ */ 25, 24)
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F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1)
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F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1)
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F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31)
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FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
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F(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8)
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F(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8)
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/* Bit 7 is Reserved (for future Opcode expansion) */
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F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
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F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
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/** @} */
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#define REG_TYPE(reg) \
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@ -491,37 +491,37 @@ REG_TYPE(src)
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/* Reserved 127:126 */
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/* src2_reg_nr same in align16 */
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FD20(3src_a1_src2_subreg_nr,/* 4+ */ 117, 113, /* 12+ */ 119, 115, /* 20+ */ 119, 115, -1)
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FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ 113, 112, devinfo->ver >= 10)
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FC(3src_a1_src2_hstride, /* 9+ */ 112, 111, /* 12+ */ 113, 112, devinfo->ver >= 10)
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/* Reserved 110:109. src2 vstride is an implied parameter */
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FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ 82, 80, devinfo->ver >= 10)
|
||||
FC(3src_a1_src2_hw_type, /* 9+ */ 108, 106, /* 12+ */ 82, 80, devinfo->ver >= 10)
|
||||
/* Reserved 105 */
|
||||
/* src1_reg_nr same in align16 */
|
||||
FD20(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ 103, 99, /* 20+ */ 103, 99, -1)
|
||||
FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ 97, 96, devinfo->ver >= 10)
|
||||
FC(3src_a1_src1_hstride, /* 9+ */ 91, 90, /* 12+ */ 97, 96, devinfo->ver >= 10)
|
||||
FDC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->ver >= 10)
|
||||
FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ 90, 88, devinfo->ver >= 10)
|
||||
FC(3src_a1_src1_hw_type, /* 9+ */ 87, 85, /* 12+ */ 90, 88, devinfo->ver >= 10)
|
||||
/* Reserved 84 */
|
||||
/* src0_reg_nr same in align16 */
|
||||
FD20(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ 71, 67, /* 20+ */ 71, 67, -1)
|
||||
FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ 65, 64, devinfo->ver >= 10)
|
||||
FC(3src_a1_src0_hstride, /* 9+ */ 70, 69, /* 12+ */ 65, 64, devinfo->ver >= 10)
|
||||
FDC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->ver >= 10)
|
||||
FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ 42, 40, devinfo->ver >= 10)
|
||||
FC(3src_a1_src0_hw_type, /* 9+ */ 66, 64, /* 12+ */ 42, 40, devinfo->ver >= 10)
|
||||
/* dst_reg_nr same in align16 */
|
||||
FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ 55, 54, devinfo->ver >= 10)
|
||||
FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ 54, 51, devinfo->ver >= 10) /* aliases dst_subreg_nr */
|
||||
FC(3src_a1_dst_subreg_nr, /* 9+ */ 55, 54, /* 12+ */ 55, 54, devinfo->ver >= 10)
|
||||
FC(3src_a1_special_acc, /* 9+ */ 55, 52, /* 12+ */ 54, 51, devinfo->ver >= 10) /* aliases dst_subreg_nr */
|
||||
/* Reserved 51:50 */
|
||||
FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ 48, 48, devinfo->ver >= 10)
|
||||
FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ 38, 36, devinfo->ver >= 10)
|
||||
FC(3src_a1_dst_hstride, /* 9+ */ 49, 49, /* 12+ */ 48, 48, devinfo->ver >= 10)
|
||||
FC(3src_a1_dst_hw_type, /* 9+ */ 48, 46, /* 12+ */ 38, 36, devinfo->ver >= 10)
|
||||
FI(3src_a1_src2_reg_file, /* 4+ */ -1, -1, /* 8+ */ 45, 45, /* 12+ */ 47, 114)
|
||||
FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ 98, 98, devinfo->ver >= 10)
|
||||
FC(3src_a1_src1_reg_file, /* 9+ */ 44, 44, /* 12+ */ 98, 98, devinfo->ver >= 10)
|
||||
FI(3src_a1_src0_reg_file, /* 4+ */ -1, -1, /* 8+ */ 43, 43, /* 12+ */ 46, 66)
|
||||
|
||||
F(3src_a1_src2_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47)
|
||||
F(3src_a1_src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46)
|
||||
F(3src_a1_src2_is_imm, /* 9+ */ -1, -1, /* 12+ */ 47, 47)
|
||||
F(3src_a1_src0_is_imm, /* 9+ */ -1, -1, /* 12+ */ 46, 46)
|
||||
|
||||
/* Source Modifier fields same in align16 */
|
||||
FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ 50, 50, devinfo->ver >= 10)
|
||||
FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver >= 10)
|
||||
FC(3src_a1_dst_reg_file, /* 9+ */ 36, 36, /* 12+ */ 50, 50, devinfo->ver >= 10)
|
||||
FC(3src_a1_exec_type, /* 9+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver >= 10)
|
||||
/* Fields below this same in align16 */
|
||||
/** @} */
|
||||
|
||||
|
|
@ -612,27 +612,27 @@ brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
|
|||
* Three-source systolic instructions:
|
||||
* @{
|
||||
*/
|
||||
F(dpas_3src_src2_reg_nr, /* 4+ */ -1, -1, /* 12+ */ 127, 120)
|
||||
F(dpas_3src_src2_subreg_nr, /* 4+ */ -1, -1, /* 12+ */ 119, 115)
|
||||
F(dpas_3src_src2_reg_file, /* 4+ */ -1, -1, /* 12+ */ 114, 114)
|
||||
F(dpas_3src_src1_reg_nr, /* 4+ */ -1, -1, /* 12+ */ 111, 104)
|
||||
F(dpas_3src_src1_subreg_nr, /* 4+ */ -1, -1, /* 12+ */ 103, 99)
|
||||
F(dpas_3src_src1_reg_file, /* 4+ */ -1, -1, /* 12+ */ 98, 98)
|
||||
F(dpas_3src_src1_hw_type, /* 4+ */ -1, -1, /* 12+ */ 90, 88)
|
||||
F(dpas_3src_src1_subbyte, /* 4+ */ -1, -1, /* 12+ */ 87, 86)
|
||||
F(dpas_3src_src2_subbyte, /* 4+ */ -1, -1, /* 12+ */ 85, 84)
|
||||
F(dpas_3src_src2_hw_type, /* 4+ */ -1, -1, /* 12+ */ 82, 80)
|
||||
F(dpas_3src_src0_reg_nr, /* 4+ */ -1, -1, /* 12+ */ 79, 72)
|
||||
F(dpas_3src_src0_subreg_nr, /* 4+ */ -1, -1, /* 12+ */ 71, 67)
|
||||
F(dpas_3src_src0_reg_file, /* 4+ */ -1, -1, /* 12+ */ 66, 66)
|
||||
F(dpas_3src_dst_reg_nr, /* 4+ */ -1, -1, /* 12+ */ 63, 56)
|
||||
F(dpas_3src_dst_subreg_nr, /* 4+ */ -1, -1, /* 12+ */ 55, 51)
|
||||
F(dpas_3src_dst_reg_file, /* 4+ */ -1, -1, /* 12+ */ 50, 50)
|
||||
F(dpas_3src_sdepth, /* 4+ */ -1, -1, /* 12+ */ 49, 48)
|
||||
F(dpas_3src_rcount, /* 4+ */ -1, -1, /* 12+ */ 45, 43)
|
||||
F(dpas_3src_src0_hw_type, /* 4+ */ -1, -1, /* 12+ */ 42, 40)
|
||||
F(dpas_3src_exec_type, /* 4+ */ -1, -1, /* 12+ */ 39, 39)
|
||||
F(dpas_3src_dst_hw_type, /* 4+ */ -1, -1, /* 12+ */ 38, 36)
|
||||
F(dpas_3src_src2_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 127, 120)
|
||||
F(dpas_3src_src2_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 119, 115)
|
||||
F(dpas_3src_src2_reg_file, /* 9+ */ -1, -1, /* 12+ */ 114, 114)
|
||||
F(dpas_3src_src1_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 111, 104)
|
||||
F(dpas_3src_src1_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 103, 99)
|
||||
F(dpas_3src_src1_reg_file, /* 9+ */ -1, -1, /* 12+ */ 98, 98)
|
||||
F(dpas_3src_src1_hw_type, /* 9+ */ -1, -1, /* 12+ */ 90, 88)
|
||||
F(dpas_3src_src1_subbyte, /* 9+ */ -1, -1, /* 12+ */ 87, 86)
|
||||
F(dpas_3src_src2_subbyte, /* 9+ */ -1, -1, /* 12+ */ 85, 84)
|
||||
F(dpas_3src_src2_hw_type, /* 9+ */ -1, -1, /* 12+ */ 82, 80)
|
||||
F(dpas_3src_src0_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 79, 72)
|
||||
F(dpas_3src_src0_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 71, 67)
|
||||
F(dpas_3src_src0_reg_file, /* 9+ */ -1, -1, /* 12+ */ 66, 66)
|
||||
F(dpas_3src_dst_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 63, 56)
|
||||
F(dpas_3src_dst_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 55, 51)
|
||||
F(dpas_3src_dst_reg_file, /* 9+ */ -1, -1, /* 12+ */ 50, 50)
|
||||
F(dpas_3src_sdepth, /* 9+ */ -1, -1, /* 12+ */ 49, 48)
|
||||
F(dpas_3src_rcount, /* 9+ */ -1, -1, /* 12+ */ 45, 43)
|
||||
F(dpas_3src_src0_hw_type, /* 9+ */ -1, -1, /* 12+ */ 42, 40)
|
||||
F(dpas_3src_exec_type, /* 9+ */ -1, -1, /* 12+ */ 39, 39)
|
||||
F(dpas_3src_dst_hw_type, /* 9+ */ -1, -1, /* 12+ */ 38, 36)
|
||||
/** @} */
|
||||
|
||||
#define REG_TYPE(reg) \
|
||||
|
|
@ -710,16 +710,16 @@ brw_inst_jip(const struct intel_device_info *devinfo, const brw_inst *inst)
|
|||
* SEND instructions:
|
||||
* @{
|
||||
*/
|
||||
F(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ 42, 40)
|
||||
F(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1)
|
||||
F(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ 48, 48)
|
||||
F(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ 49, 49)
|
||||
F(send_ex_desc_ia_subreg_nr, /* 9+ */ 82, 80, /* 12+ */ 42, 40)
|
||||
F(send_src0_address_mode, /* 9+ */ 79, 79, /* 12+ */ -1, -1)
|
||||
F(send_sel_reg32_desc, /* 9+ */ 77, 77, /* 12+ */ 48, 48)
|
||||
F(send_sel_reg32_ex_desc, /* 9+ */ 61, 61, /* 12+ */ 49, 49)
|
||||
F8(send_src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 66, 66)
|
||||
F(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ 111, 104)
|
||||
FC(send_src1_len, /* 4+ */ -1, -1, /* 12+ */ 103, 99, devinfo->verx10 >= 125)
|
||||
F(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ 98, 98)
|
||||
F(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50)
|
||||
FC(send_ex_bso, /* 4+ */ -1, -1, /* 12+ */ 39, 39, devinfo->verx10 >= 125)
|
||||
F(send_src1_reg_nr, /* 9+ */ 51, 44, /* 12+ */ 111, 104)
|
||||
FC(send_src1_len, /* 9+ */ -1, -1, /* 12+ */ 103, 99, devinfo->verx10 >= 125)
|
||||
F(send_src1_reg_file, /* 9+ */ 36, 36, /* 12+ */ 98, 98)
|
||||
F(send_dst_reg_file, /* 9+ */ 35, 35, /* 12+ */ 50, 50)
|
||||
FC(send_ex_bso, /* 9+ */ -1, -1, /* 12+ */ 39, 39, devinfo->verx10 >= 125)
|
||||
/** @} */
|
||||
|
||||
/* Message descriptor bits */
|
||||
|
|
@ -873,7 +873,7 @@ brw_inst_sends_ex_desc(const struct intel_device_info *devinfo,
|
|||
* Fields for SEND messages:
|
||||
* @{
|
||||
*/
|
||||
F(eot, /* 4+ */ 127, 127, /* 12+ */ 34, 34)
|
||||
F(eot, /* 9+ */ 127, 127, /* 12+ */ 34, 34)
|
||||
FF(mlen,
|
||||
/* 4: */ 119, 116,
|
||||
/* 4.5: */ 119, 116,
|
||||
|
|
@ -900,7 +900,7 @@ FF(header_present,
|
|||
/* 8: */ 115, 115,
|
||||
/* 12: */ MD12(19), MD12(19),
|
||||
/* 20: */ MD12(19), MD12(19))
|
||||
F(gateway_notify, /* 4+ */ MD(16), MD(15), /* 12+ */ -1, -1)
|
||||
F(gateway_notify, /* 9+ */ MD(16), MD(15), /* 12+ */ -1, -1)
|
||||
FD(function_control,
|
||||
/* 4: */ 111, 96,
|
||||
/* 4.5: */ 111, 96,
|
||||
|
|
@ -953,7 +953,7 @@ FF(urb_per_slot_offset,
|
|||
/* 8: */ MD(17), MD(17),
|
||||
/* 12: */ MD12(17), MD12(17),
|
||||
/* 20: */ MD12(17), MD12(17))
|
||||
F(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15))
|
||||
F(urb_channel_mask_present, /* 9+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15))
|
||||
FF(urb_swizzle_control,
|
||||
/* 4: */ MD(11), MD(10),
|
||||
/* 4.5: */ MD(11), MD(10),
|
||||
|
|
@ -1011,14 +1011,14 @@ FD(sampler,
|
|||
/* 7: */ MD(11), MD(8),
|
||||
/* 8: */ MD(11), MD(8),
|
||||
/* 12: */ MD12(11), MD12(11), MD12(10), MD12(8))
|
||||
F(binding_table_index, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /* also used by other messages */
|
||||
F(binding_table_index, /* 9+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /* also used by other messages */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Data port message function control bits:
|
||||
* @{
|
||||
*/
|
||||
F(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18))
|
||||
F(dp_category, /* 9+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18))
|
||||
|
||||
/* Gfx4-5 store fields in different bits for read/write messages. */
|
||||
FF(dp_read_msg_type,
|
||||
|
|
@ -1078,10 +1078,10 @@ FD(dp_msg_control,
|
|||
* Scratch message bits:
|
||||
* @{
|
||||
*/
|
||||
F(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17)) /* 0 = read, 1 = write */
|
||||
F(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1) /* 0 = OWord, 1 = DWord */
|
||||
F(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15))
|
||||
F(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
|
||||
F(scratch_read_write, /* 9+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17)) /* 0 = read, 1 = write */
|
||||
F(scratch_type, /* 9+ */ MD(16), MD(16), /* 12+ */ -1, -1) /* 0 = OWord, 1 = DWord */
|
||||
F(scratch_invalidate_after_read, /* 9+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15))
|
||||
F(scratch_block_size, /* 9+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
|
||||
FD(scratch_addr_offset,
|
||||
/* 4: */ -1, -1,
|
||||
/* 4.5: */ -1, -1,
|
||||
|
|
@ -1105,28 +1105,28 @@ FF(rt_last,
|
|||
/* 8: */ MD(12), MD(12),
|
||||
/* 12: */ MD12(12), MD12(12),
|
||||
/* 20: */ MD12(12), MD12(12))
|
||||
F(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
|
||||
F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8))
|
||||
F(rt_slot_group, /* 9+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
|
||||
F(rt_message_type, /* 9+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Thread Spawn message function control bits:
|
||||
* @{
|
||||
*/
|
||||
FC(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1, devinfo->ver < 11)
|
||||
FC(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1, devinfo->ver < 11)
|
||||
F(ts_opcode, /* 4+ */ MD( 0), MD( 0), /* 12+ */ MD12(0), MD12(0))
|
||||
FC(ts_resource_select, /* 9+ */ MD( 4), MD( 4), /* 12+ */ -1, -1, devinfo->ver < 11)
|
||||
FC(ts_request_type, /* 9+ */ MD( 1), MD( 1), /* 12+ */ -1, -1, devinfo->ver < 11)
|
||||
F(ts_opcode, /* 9+ */ MD( 0), MD( 0), /* 12+ */ MD12(0), MD12(0))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Pixel Interpolator message function control bits:
|
||||
* @{
|
||||
*/
|
||||
F(pi_simd_mode, /* 4+ */ MD(16), MD(16), /* 12+ */ MD12(16), MD12(16))
|
||||
F(pi_nopersp, /* 4+ */ MD(14), MD(14), /* 12+ */ MD12(14), MD12(14))
|
||||
F(pi_message_type, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
|
||||
F(pi_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
|
||||
F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0))
|
||||
F(pi_simd_mode, /* 9+ */ MD(16), MD(16), /* 12+ */ MD12(16), MD12(16))
|
||||
F(pi_nopersp, /* 9+ */ MD(14), MD(14), /* 12+ */ MD12(14), MD12(14))
|
||||
F(pi_message_type, /* 9+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
|
||||
F(pi_slot_group, /* 9+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
|
||||
F(pi_message_data, /* 9+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
|
@ -1460,7 +1460,7 @@ brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
|
|||
inst->data = (inst->data & ~mask) | (value << low);
|
||||
}
|
||||
|
||||
#define FC(name, high, low, gfx12_high, gfx12_low, assertions) \
|
||||
#define FC(name, hi9, lo9, hi12, lo12, assertions) \
|
||||
static inline void \
|
||||
brw_compact_inst_set_##name(const struct \
|
||||
intel_device_info *devinfo, \
|
||||
|
|
@ -1468,9 +1468,9 @@ brw_compact_inst_set_##name(const struct \
|
|||
{ \
|
||||
assert(assertions); \
|
||||
if (devinfo->ver >= 12) \
|
||||
brw_compact_inst_set_bits(inst, gfx12_high, gfx12_low, v); \
|
||||
brw_compact_inst_set_bits(inst, hi12, lo12, v); \
|
||||
else \
|
||||
brw_compact_inst_set_bits(inst, high, low, v); \
|
||||
brw_compact_inst_set_bits(inst, hi9, lo9, v); \
|
||||
} \
|
||||
static inline unsigned \
|
||||
brw_compact_inst_##name(const struct intel_device_info *devinfo, \
|
||||
|
|
@ -1478,16 +1478,15 @@ brw_compact_inst_##name(const struct intel_device_info *devinfo, \
|
|||
{ \
|
||||
assert(assertions); \
|
||||
if (devinfo->ver >= 12) \
|
||||
return brw_compact_inst_bits(inst, gfx12_high, gfx12_low); \
|
||||
return brw_compact_inst_bits(inst, hi12, lo12); \
|
||||
else \
|
||||
return brw_compact_inst_bits(inst, high, low); \
|
||||
return brw_compact_inst_bits(inst, hi9, lo9); \
|
||||
}
|
||||
|
||||
/* A simple macro for fields which stay in the same place on all generations
|
||||
* except for Gfx12.
|
||||
*/
|
||||
#define F(name, high, low, gfx12_high, gfx12_low) \
|
||||
FC(name, high, low, gfx12_high, gfx12_low, true)
|
||||
#define F(name, hi9, lo9, hi12, lo12) FC(name, hi9, lo9, hi12, lo12, true)
|
||||
|
||||
/* A macro for fields which moved to several different locations
|
||||
* across generations.
|
||||
|
|
@ -1560,20 +1559,20 @@ brw_compact_inst_##name(const struct intel_device_info *devinfo, \
|
|||
} \
|
||||
}
|
||||
|
||||
F(src1_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56)
|
||||
F(src0_reg_nr, /* 4+ */ 55, 48, /* 12+ */ 47, 40)
|
||||
F(src1_reg_nr, /* 9+ */ 63, 56, /* 12+ */ 63, 56)
|
||||
F(src0_reg_nr, /* 9+ */ 55, 48, /* 12+ */ 47, 40)
|
||||
F20(dst_reg_nr, /* 4+ */ 47, 40, /* 8+ */ 47, 40, /* 12+ */ 23, 16, /* 20+ */ 39, 32)
|
||||
F(src1_index, /* 4+ */ 39, 35, /* 12+ */ 55, 52)
|
||||
F(src1_index, /* 9+ */ 39, 35, /* 12+ */ 55, 52)
|
||||
F20(src0_index, /* 4+ */ 34, 30, /* 8+ */ 34, 30, /* 12+ */ 51, 48, /* 20+ */ 25, 23)
|
||||
F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */
|
||||
F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */
|
||||
F(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1)
|
||||
F(cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */
|
||||
F(cond_modifier, /* 9+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */
|
||||
F(acc_wr_control, /* 9+ */ 23, 23, /* 12+ */ -1, -1)
|
||||
F20(subreg_index, /* 4+ */ 22, 18, /* 8+ */ 22, 18, /* 12+ */ 39, 35, /* 20+ */ 51, 48)
|
||||
FD20(datatype_index, /* 4+ */ 17, 13, /* 8+ */ 17, 13, /* 12+ */ 34, 30, /* 20+ */ 28, 26, 31, 30)
|
||||
F20(control_index, /* 4+ */ 12, 8, /* 8+ */ 12, 8, /* 12+ */ 28, 24, /* 20+ */ 22, 18)
|
||||
F20(swsb, /* 4+ */ -1, -1, /* 8+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
|
||||
F(debug_control, /* 4+ */ 7, 7, /* 12+ */ 7, 7)
|
||||
F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */
|
||||
F(debug_control, /* 9+ */ 7, 7, /* 12+ */ 7, 7)
|
||||
F(hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */
|
||||
|
||||
static inline unsigned
|
||||
brw_compact_inst_imm(const struct intel_device_info *devinfo,
|
||||
|
|
@ -1591,18 +1590,18 @@ brw_compact_inst_imm(const struct intel_device_info *devinfo,
|
|||
* Compacted three-source instructions:
|
||||
* @{
|
||||
*/
|
||||
F(3src_src2_reg_nr, /* 4+ */ 63, 57, /* 12+ */ 55, 48)
|
||||
F(3src_src1_reg_nr, /* 4+ */ 56, 50, /* 12+ */ 63, 56)
|
||||
F(3src_src0_reg_nr, /* 4+ */ 49, 43, /* 12+ */ 47, 40)
|
||||
F(3src_src2_subreg_nr, /* 4+ */ 42, 40, /* 12+ */ -1, -1)
|
||||
F(3src_src1_subreg_nr, /* 4+ */ 39, 37, /* 12+ */ -1, -1)
|
||||
F(3src_src0_subreg_nr, /* 4+ */ 36, 34, /* 12+ */ -1, -1)
|
||||
F(3src_src2_rep_ctrl, /* 4+ */ 33, 33, /* 12+ */ -1, -1)
|
||||
F(3src_src1_rep_ctrl, /* 4+ */ 32, 32, /* 12+ */ -1, -1)
|
||||
F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1)
|
||||
F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 7, 7)
|
||||
F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29)
|
||||
F(3src_src0_rep_ctrl, /* 4+ */ 28, 28, /* 12+ */ -1, -1)
|
||||
F(3src_src2_reg_nr, /* 9+ */ 63, 57, /* 12+ */ 55, 48)
|
||||
F(3src_src1_reg_nr, /* 9+ */ 56, 50, /* 12+ */ 63, 56)
|
||||
F(3src_src0_reg_nr, /* 9+ */ 49, 43, /* 12+ */ 47, 40)
|
||||
F(3src_src2_subreg_nr, /* 9+ */ 42, 40, /* 12+ */ -1, -1)
|
||||
F(3src_src1_subreg_nr, /* 9+ */ 39, 37, /* 12+ */ -1, -1)
|
||||
F(3src_src0_subreg_nr, /* 9+ */ 36, 34, /* 12+ */ -1, -1)
|
||||
F(3src_src2_rep_ctrl, /* 9+ */ 33, 33, /* 12+ */ -1, -1)
|
||||
F(3src_src1_rep_ctrl, /* 9+ */ 32, 32, /* 12+ */ -1, -1)
|
||||
F(3src_saturate, /* 9+ */ 31, 31, /* 12+ */ -1, -1)
|
||||
F(3src_debug_control, /* 9+ */ 30, 30, /* 12+ */ 7, 7)
|
||||
F(3src_cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
|
||||
F(3src_src0_rep_ctrl, /* 9+ */ 28, 28, /* 12+ */ -1, -1)
|
||||
/* Reserved */
|
||||
F20(3src_dst_reg_nr, /* 4+ */ 18, 12, /* 8+ */ 18, 12, /* 12+ */ 23, 16, /* 20+ */ 39, 32)
|
||||
F20(3src_source_index, /* 4+ */ -1, -1, /* 8+ */ 11, 10, /* 12+ */ 34, 30, /* 20+ */ 25, 22)
|
||||
|
|
@ -1610,7 +1609,7 @@ FD20(3src_subreg_index, /* 4+ */ -1, -1, /* 8+ */ -1, -1, /* 12+ */ 39, 35, /*
|
|||
F20(3src_control_index, /* 4+ */ -1, -1, /* 8+ */ 9, 8, /* 12+ */ 28, 24, /* 20+ */ 21, 18)
|
||||
F20(3src_swsb, /* 4+ */ -1, -1, /* 8+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
|
||||
/* Bit 7 is Reserved (for future Opcode expansion) */
|
||||
F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0)
|
||||
F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
|
||||
/** @} */
|
||||
|
||||
#undef F
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue