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freedreno/ir3: add MOD support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
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cab3cb1d71
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1 changed files with 12 additions and 8 deletions
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@ -1995,10 +1995,10 @@ trans_umul(const struct instr_translater *t,
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}
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}
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/*
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/*
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* IDIV / UDIV / UMOD
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* IDIV / UDIV / MOD / UMOD
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*
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*
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* See NV50LegalizeSSA::handleDIV for the origin of this implementation. For
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* See NV50LegalizeSSA::handleDIV for the origin of this implementation. For
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* UMOD, it becomes a - UDIV(a, modulus) * modulus.
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* MOD/UMOD, it becomes a - [IU]DIV(a, modulus) * modulus.
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*/
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*/
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static void
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static void
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trans_idiv(const struct instr_translater *t,
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trans_idiv(const struct instr_translater *t,
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@ -2014,9 +2014,12 @@ trans_idiv(const struct instr_translater *t,
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struct tgsi_src_register *af_src, *bf_src, *q_src, *r_src, *a_src, *b_src;
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struct tgsi_src_register *af_src, *bf_src, *q_src, *r_src, *a_src, *b_src;
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struct tgsi_src_register negative_2, thirty_one;
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struct tgsi_src_register negative_2, thirty_one;
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type_t src_type;
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type_t src_type = t->tgsi_opc == TGSI_OPCODE_IDIV ?
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if (t->tgsi_opc == TGSI_OPCODE_IDIV || t->tgsi_opc == TGSI_OPCODE_MOD)
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get_stype(ctx) : get_utype(ctx);
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src_type = get_stype(ctx);
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else
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src_type = get_utype(ctx);
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af_src = get_internal_temp(ctx, &af_dst);
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af_src = get_internal_temp(ctx, &af_dst);
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bf_src = get_internal_temp(ctx, &bf_dst);
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bf_src = get_internal_temp(ctx, &bf_dst);
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@ -2028,7 +2031,7 @@ trans_idiv(const struct instr_translater *t,
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get_immediate(ctx, &negative_2, -2);
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get_immediate(ctx, &negative_2, -2);
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get_immediate(ctx, &thirty_one, 31);
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get_immediate(ctx, &thirty_one, 31);
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if (t->tgsi_opc == TGSI_OPCODE_UMOD)
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if (t->tgsi_opc == TGSI_OPCODE_MOD || t->tgsi_opc == TGSI_OPCODE_UMOD)
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premod_dst = &q_dst;
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premod_dst = &q_dst;
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/* cov.[us]32f32 af, numerator */
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/* cov.[us]32f32 af, numerator */
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@ -2044,7 +2047,7 @@ trans_idiv(const struct instr_translater *t,
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vectorize(ctx, instr, &bf_dst, 1, b, 0);
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vectorize(ctx, instr, &bf_dst, 1, b, 0);
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/* Get the absolute values for IDIV */
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/* Get the absolute values for IDIV */
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if (t->tgsi_opc == TGSI_OPCODE_IDIV) {
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if (type_sint(src_type)) {
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/* absneg.f af, (abs)af */
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/* absneg.f af, (abs)af */
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instr = instr_create(ctx, 2, OPC_ABSNEG_F);
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instr = instr_create(ctx, 2, OPC_ABSNEG_F);
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vectorize(ctx, instr, &af_dst, 1, af_src, IR3_REG_ABS);
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vectorize(ctx, instr, &af_dst, 1, af_src, IR3_REG_ABS);
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@ -2151,7 +2154,7 @@ trans_idiv(const struct instr_translater *t,
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instr->cat2.condition = IR3_COND_GE;
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instr->cat2.condition = IR3_COND_GE;
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vectorize(ctx, instr, &r_dst, 2, r_src, 0, b_src, 0);
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vectorize(ctx, instr, &r_dst, 2, r_src, 0, b_src, 0);
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if (t->tgsi_opc != TGSI_OPCODE_IDIV) {
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if (type_uint(src_type)) {
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/* add.u dst, q, r */
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/* add.u dst, q, r */
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instr = instr_create(ctx, 2, OPC_ADD_U);
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instr = instr_create(ctx, 2, OPC_ADD_U);
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vectorize(ctx, instr, premod_dst, 2, q_src, 0, r_src, 0);
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vectorize(ctx, instr, premod_dst, 2, q_src, 0, r_src, 0);
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@ -2181,7 +2184,7 @@ trans_idiv(const struct instr_translater *t,
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vectorize(ctx, instr, premod_dst, 3, b_src, 0, r_src, 0, q_src, 0);
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vectorize(ctx, instr, premod_dst, 3, b_src, 0, r_src, 0, q_src, 0);
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}
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}
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if (t->tgsi_opc == TGSI_OPCODE_UMOD) {
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if (t->tgsi_opc == TGSI_OPCODE_MOD || t->tgsi_opc == TGSI_OPCODE_UMOD) {
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/* The division result will have ended up in q. */
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/* The division result will have ended up in q. */
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/* mull.u r, q, b */
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/* mull.u r, q, b */
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@ -2365,6 +2368,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
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INSTR(UMUL, trans_umul),
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INSTR(UMUL, trans_umul),
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INSTR(UDIV, trans_idiv),
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INSTR(UDIV, trans_idiv),
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INSTR(IDIV, trans_idiv),
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INSTR(IDIV, trans_idiv),
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INSTR(MOD, trans_idiv),
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INSTR(UMOD, trans_idiv),
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INSTR(UMOD, trans_idiv),
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INSTR(SHL, instr_cat2, .opc = OPC_SHL_B),
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INSTR(SHL, instr_cat2, .opc = OPC_SHL_B),
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INSTR(USHR, instr_cat2, .opc = OPC_SHR_B),
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INSTR(USHR, instr_cat2, .opc = OPC_SHR_B),
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