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radeon/vcn: increase encoder dpb size

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Base the number of reconstructed pictures the encoder allocates based on
the number of reference pictures to be used for encoding. Also move the
calculation and allocation of reconstructed pictures to VCN 1, from VCN
2.

v2: Add back the accidentally deleted
'two_pass_search_center_map_offset' (Boyuan)

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13915>
This commit is contained in:
Thong Thai 2021-11-08 14:09:10 -05:00 • committed by Marge Bot
parent 31b033eec2
commit ad3ed91b1f
4 changed files with 67 additions and 57 deletions
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35
src/gallium/drivers/radeon/radeon_vcn_enc.c
View file

@ -389,6 +389,39 @@ static void radeon_enc_get_feedback(struct pipe_video_codec *encoder, void *feed
FREE(fb);
}
static int setup_dpb(struct radeon_encoder *enc, enum pipe_format buffer_format)
{
uint32_t aligned_width = align(enc->base.width, 16);
uint32_t aligned_height = align(enc->base.height, 16);
uint32_t rec_luma_pitch = align(aligned_width, enc->alignment);
int luma_size = rec_luma_pitch * align(aligned_height, enc->alignment);
if (buffer_format == PIPE_FORMAT_P010)
luma_size *= 2;
int chroma_size = align(luma_size / 2, enc->alignment);
int offset = 0;
uint32_t num_reconstructed_pictures = enc->base.max_references + 1;
assert(num_reconstructed_pictures <= RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES);
int i;
for (i = 0; i < num_reconstructed_pictures; i++) {
enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = offset;
offset += luma_size;
enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = offset;
offset += chroma_size;
}
for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = 0;
enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = 0;
}
enc->enc_pic.ctx_buf.num_reconstructed_pictures = num_reconstructed_pictures;
enc->dpb_size = offset;
return offset;
}
struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
const struct pipe_video_codec *templ,
struct radeon_winsys *ws,
@ -454,6 +487,8 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
cpb_size = cpb_size * enc->cpb_num;
tmp_buf->destroy(tmp_buf);
cpb_size += setup_dpb(enc, templat.buffer_format);
if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't create CPB buffer.\n");
goto error;

1
src/gallium/drivers/radeon/radeon_vcn_enc.h
View file

@ -553,6 +553,7 @@ struct radeon_encoder {
bool emulation_prevention;
bool need_feedback;
unsigned dpb_size;
};
void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,

43
src/gallium/drivers/radeon/radeon_vcn_enc_1_2.c
View file

@ -1034,27 +1034,46 @@ static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
static void radeon_enc_ctx(struct radeon_encoder *enc)
{
enc->enc_pic.ctx_buf.swizzle_mode = 0;
enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment);
enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment);
enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
uint32_t aligned_width = enc->enc_pic.session_init.aligned_picture_width;
uint32_t aligned_height = enc->enc_pic.session_init.aligned_picture_height;
enc->enc_pic.ctx_buf.rec_luma_pitch = align(aligned_width, enc->alignment);
enc->enc_pic.ctx_buf.rec_chroma_pitch = align(aligned_width, enc->alignment);
int luma_size = enc->enc_pic.ctx_buf.rec_luma_pitch * align(aligned_height, enc->alignment);
if (enc->enc_pic.bit_depth_luma_minus8 == 2)
luma_size *= 2;
int chroma_size = align(luma_size / 2, enc->alignment);
int offset = 0;
for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
offset += luma_size;
offset += chroma_size;
}
assert(offset == enc->dpb_size);
RADEON_ENC_BEGIN(enc->cmd.ctx);
RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
/* reconstructed_picture_1_luma_offset */
RADEON_ENC_CS(0x00000000);
/* reconstructed_picture_1_chroma_offset */
RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16));
/* reconstructed_picture_2_luma_offset */
RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2);
/* reconstructed_picture_2_chroma_offset */
RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2);
for (int i = 0; i < 136; i++)
for (int i = 0; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
}
// 2: 1 pre encode pitch * 2 (luma + chroma)
// 68: 34 pre encode reconstructed pics * 2 (luma + chroma offsets)
// 2: 1 pre encode input pic * 2 (luma + chroma)
//----
// 72
for (int i = 0; i < 72; i++)
RADEON_ENC_CS(0x00000000);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);

45
src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
View file

@ -428,50 +428,6 @@ static void radeon_enc_output_format(struct radeon_encoder *enc)
RADEON_ENC_END();
}
static void radeon_enc_ctx(struct radeon_encoder *enc)
{
enc->enc_pic.ctx_buf.swizzle_mode = 0;
uint32_t aligned_width = enc->enc_pic.session_init.aligned_picture_width;
uint32_t aligned_height = enc->enc_pic.session_init.aligned_picture_height;
enc->enc_pic.ctx_buf.rec_luma_pitch = align(aligned_width, enc->alignment);
enc->enc_pic.ctx_buf.rec_chroma_pitch = align(aligned_width, enc->alignment);
int luma_size = enc->enc_pic.ctx_buf.rec_luma_pitch * align(aligned_height, enc->alignment);
if (enc->enc_pic.bit_depth_luma_minus8 == 2)
luma_size *= 2;
int chroma_size = align(luma_size / 2, enc->alignment);
int offset = 0;
enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2;
for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = offset;
offset += luma_size;
enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = offset;
offset += chroma_size;
}
enc->enc_pic.ctx_buf.two_pass_search_center_map_offset = 0;
RADEON_ENC_BEGIN(enc->cmd.ctx);
RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures);
for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) {
RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset);
}
for (int i = 0; i < 136; i++)
RADEON_ENC_CS(0x00000000);
RADEON_ENC_CS(enc->enc_pic.ctx_buf.two_pass_search_center_map_offset);
RADEON_ENC_END();
}
static void encode(struct radeon_encoder *enc)
{
enc->session_info(enc);
@ -495,7 +451,6 @@ void radeon_enc_2_0_init(struct radeon_encoder *enc)
{
radeon_enc_1_2_init(enc);
enc->encode = encode;
enc->ctx = radeon_enc_ctx;
enc->input_format = radeon_enc_input_format;
enc->output_format = radeon_enc_output_format;