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zink: do not lower gs-intrinsics

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We don't use the counters for anything useful, so let's drop this
lowering pass.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20135>
This commit is contained in:
Erik Faye-Lund 2022-12-05 15:25:55 +01:00 • committed by Marge Bot
parent 7244d88516
commit ad26d29adc
2 changed files with 4 additions and 9 deletions
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8
src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
View file

@ -3292,7 +3292,7 @@ emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr)
emit_load_uint_input(ctx, intr, &ctx->sample_mask_in_var, "gl_SampleMaskIn", SpvBuiltInSampleMask);
break;
case nir_intrinsic_emit_vertex_with_counter:
case nir_intrinsic_emit_vertex:
/* geometry shader emits copied xfb outputs just prior to EmitVertex(),
* since that's the end of the shader
*/
@ -3303,11 +3303,7 @@ emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr)
ctx->nir->info.stage == MESA_SHADER_GEOMETRY && util_bitcount(ctx->nir->info.gs.active_stream_mask) > 1);
break;
case nir_intrinsic_set_vertex_and_primitive_count:
/* do nothing */
break;
case nir_intrinsic_end_primitive_with_counter:
case nir_intrinsic_end_primitive:
spirv_builder_end_primitive(&ctx->builder, nir_intrinsic_stream_id(intr),
ctx->nir->info.stage == MESA_SHADER_GEOMETRY && util_bitcount(ctx->nir->info.gs.active_stream_mask) > 1);
break;

5
src/gallium/drivers/zink/zink_compiler.c
View file

@ -1612,7 +1612,8 @@ clamp_layer_output_instr(nir_builder *b, nir_instr *instr, void *data)
switch (instr->type) {
case nir_instr_type_intrinsic: {
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
if (intr->intrinsic != nir_intrinsic_emit_vertex_with_counter)
if (intr->intrinsic != nir_intrinsic_emit_vertex_with_counter &&
intr->intrinsic != nir_intrinsic_emit_vertex)
return false;
b->cursor = nir_before_instr(instr);
clamp_layer_output_emit(b, state);
@ -3812,8 +3813,6 @@ zink_shader_finalize(struct pipe_screen *pscreen, void *nirptr)
if (!screen->info.feats.features.shaderImageGatherExtended)
tex_opts.lower_tg4_offsets = true;
NIR_PASS_V(nir, nir_lower_tex, &tex_opts);
if (nir->info.stage == MESA_SHADER_GEOMETRY)
NIR_PASS_V(nir, nir_lower_gs_intrinsics, nir_lower_gs_intrinsics_per_stream);
optimize_nir(nir, NULL);
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
if (screen->driconf.inline_uniforms)