mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-09 17:00:13 +01:00
nak: Add a NIR texture lowering pass
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
31ecffa3a3
commit
ad01fbdda0
4 changed files with 351 additions and 0 deletions
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@ -10,6 +10,7 @@ dep_syn = dependency('syn',
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libnak_c_files = files(
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'nak.h',
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'nak_nir.c',
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'nak_nir_lower_tex.c',
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)
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libnak_rs_files = files(
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@ -533,6 +533,7 @@ nak_postprocess_nir(nir_shader *nir, const struct nak_compiler *nak)
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};
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OPT(nir, nir_lower_mem_access_bit_sizes, &mem_bit_size_options);
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OPT(nir, nak_nir_lower_tex, nak);
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OPT(nir, nir_lower_idiv, NULL);
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OPT(nir, nir_lower_int64);
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325
src/nouveau/compiler/nak_nir_lower_tex.c
Normal file
325
src/nouveau/compiler/nak_nir_lower_tex.c
Normal file
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@ -0,0 +1,325 @@
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/*
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* Copyright © 2023 Collabora, Ltd.
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* SPDX-License-Identifier: MIT
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*/
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#include "nak_private.h"
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#include "nir_builder.h"
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#include "nir_format_convert.h"
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static bool
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lower_tex(nir_builder *b, nir_tex_instr *tex, const struct nak_compiler *nak)
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{
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b->cursor = nir_before_instr(&tex->instr);
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nir_def *tex_h = NULL, *samp_h = NULL, *coord = NULL, *ms_idx = NULL;
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nir_def *offset = NULL, *lod = NULL, *bias = NULL, *min_lod = NULL;
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nir_def *ddx = NULL, *ddy = NULL, *z_cmpr = NULL;
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for (unsigned i = 0; i < tex->num_srcs; i++) {
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switch (tex->src[i].src_type) {
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case nir_tex_src_texture_handle: tex_h = tex->src[i].src.ssa; break;
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case nir_tex_src_sampler_handle: samp_h = tex->src[i].src.ssa; break;
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case nir_tex_src_coord: coord = tex->src[i].src.ssa; break;
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case nir_tex_src_ms_index: ms_idx = tex->src[i].src.ssa; break;
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case nir_tex_src_comparator: z_cmpr = tex->src[i].src.ssa; break;
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case nir_tex_src_offset: offset = tex->src[i].src.ssa; break;
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case nir_tex_src_lod: lod = tex->src[i].src.ssa; break;
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case nir_tex_src_bias: bias = tex->src[i].src.ssa; break;
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case nir_tex_src_min_lod: min_lod = tex->src[i].src.ssa; break;
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case nir_tex_src_ddx: ddx = tex->src[i].src.ssa; break;
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case nir_tex_src_ddy: ddy = tex->src[i].src.ssa; break;
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default:
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unreachable("Unsupported texture source");
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}
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}
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/* Combine sampler and texture into one if needed */
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if (samp_h != NULL && samp_h != tex_h) {
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tex_h = nir_ior(b, nir_iand_imm(b, tex_h, 0x000fffff),
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nir_iand_imm(b, samp_h, 0xfff00000));
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}
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tex_h = nir_u2u32(b, tex_h);
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/* Array index is treated separately, so pull it off if we have one. */
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nir_def *arr_idx = NULL;
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unsigned coord_components = tex->coord_components;
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if (coord && tex->is_array) {
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if (tex->op == nir_texop_lod) {
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/* The HW wants an array index. Use zero. */
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arr_idx = nir_imm_int(b, 0);
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} else {
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arr_idx = nir_channel(b, coord, --coord_components);
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/* Everything but texelFetch takes a float index
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*
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* TODO: Use F2I.U32.RNE
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*/
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if (tex->op != nir_texop_txf)
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arr_idx = nir_f2u32(b, nir_fadd_imm(b, arr_idx, 0.5));
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arr_idx = nir_umin(b, arr_idx, nir_imm_int(b, UINT16_MAX));
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}
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}
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enum nak_nir_lod_mode lod_mode = NAK_NIR_LOD_MODE_AUTO;
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if (lod != NULL) {
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nir_scalar lod_s = { .def = lod, .comp = 0 };
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if (nir_scalar_is_const(lod_s) &&
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nir_scalar_as_uint(lod_s) == 0) {
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lod_mode = NAK_NIR_LOD_MODE_ZERO;
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lod = NULL; /* We don't need this */
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} else {
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lod_mode = NAK_NIR_LOD_MODE_LOD;
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}
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} else if (bias != NULL) {
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lod_mode = NAK_NIR_LOD_MODE_BIAS;
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lod = bias;
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}
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if (min_lod != NULL) {
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switch (lod_mode) {
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case NAK_NIR_LOD_MODE_AUTO:
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lod_mode = NAK_NIR_LOD_MODE_CLAMP;
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break;
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case NAK_NIR_LOD_MODE_BIAS:
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lod_mode = NAK_NIR_LOD_MODE_BIAS_CLAMP;
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break;
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default:
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unreachable("Invalid min_lod");
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}
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min_lod = nir_f2u32(b, nir_fmax(b, nir_fmul_imm(b, min_lod, 256),
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nir_imm_float(b, 16)));
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}
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enum nak_nir_offset_mode offset_mode = NAK_NIR_OFFSET_MODE_NONE;
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if (offset != NULL) {
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/* For TG4, offsets, are packed into a single 32-bit value with 8 bits
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* per component. For all other texture instructions, offsets are
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* packed into a single at most 16-bit value with 8 bits per component.
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*/
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static const unsigned bits4[] = { 4, 4, 4, 4 };
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static const unsigned bits8[] = { 8, 8, 8, 8 };
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const unsigned *bits = tex->op == nir_texop_tg4 ? bits8 : bits4;
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offset = nir_pad_vector_imm_int(b, offset, 0, 4);
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offset = nir_format_clamp_sint(b, offset, bits);
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offset = nir_format_pack_uint(b, offset, bits, 4);
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offset_mode = NAK_NIR_OFFSET_MODE_AOFFI;
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} else if (nir_tex_instr_has_explicit_tg4_offsets(tex)) {
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uint64_t off_u64 = 0;
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for (uint8_t i = 0; i < 8; ++i) {
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uint64_t off = (uint8_t)tex->tg4_offsets[i / 2][i % 2];
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off_u64 |= off << (i * 8);
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}
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offset = nir_imm_ivec2(b, off_u64, off_u64 >> 32);
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offset_mode = NAK_NIR_OFFSET_MODE_PER_PX;
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}
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nir_def *src0[4] = { NULL, };
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nir_def *src1[4] = { NULL, };
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unsigned src0_comps = 0, src1_comps = 0;
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#define PUSH(a, x) do { \
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nir_def *val = (x); \
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assert(a##_comps < ARRAY_SIZE(a)); \
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a[a##_comps++] = val; \
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} while(0)
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if (nak->sm >= 50) {
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if (tex->op == nir_texop_txd) {
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PUSH(src0, tex_h);
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for (uint32_t i = 0; i < coord_components; i++)
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PUSH(src0, nir_channel(b, coord, i));
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if (offset != NULL) {
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nir_def *arr_off = nir_ishl_imm(b, offset, 16);
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if (arr_idx)
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arr_off = nir_ior(b, arr_off, arr_idx);
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PUSH(src0, arr_off);
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} else if (arr_idx != NULL) {
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PUSH(src0, arr_idx);
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}
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assert(ddx->num_components == coord_components);
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for (uint32_t i = 0; i < coord_components; i++) {
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PUSH(src1, nir_channel(b, ddx, i));
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PUSH(src1, nir_channel(b, ddy, i));
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}
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} else {
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if (min_lod != NULL) {
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nir_def *arr_ml = nir_ishl_imm(b, min_lod, 16);
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if (arr_idx)
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arr_ml = nir_ior(b, arr_ml, arr_idx);
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PUSH(src0, arr_ml);
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} else if (arr_idx != NULL) {
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PUSH(src0, arr_idx);
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}
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for (uint32_t i = 0; i < coord_components; i++)
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PUSH(src0, nir_channel(b, coord, i));
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PUSH(src1, tex_h);
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if (ms_idx != NULL)
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PUSH(src1, ms_idx);
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if (lod != NULL)
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PUSH(src1, lod);
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if (offset_mode == NAK_NIR_OFFSET_MODE_AOFFI) {
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PUSH(src1, offset);
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} else if (offset_mode == NAK_NIR_OFFSET_MODE_PER_PX) {
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PUSH(src1, nir_channel(b, offset, 0));
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PUSH(src1, nir_channel(b, offset, 1));
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}
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if (z_cmpr != NULL)
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PUSH(src1, z_cmpr);
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}
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} else {
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unreachable("Unsupported shader model");
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}
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nir_def *vec_srcs[2] = {
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nir_vec(b, src0, src0_comps),
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nir_vec(b, src1, src1_comps),
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};
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tex->src[0].src_type = nir_tex_src_backend1;
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nir_src_rewrite(&tex->src[0].src, vec_srcs[0]);
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tex->src[1].src_type = nir_tex_src_backend2;
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nir_src_rewrite(&tex->src[1].src, vec_srcs[1]);
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/* Remove any extras */
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while (tex->num_srcs > 2)
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nir_tex_instr_remove_src(tex, tex->num_srcs - 1);
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struct nak_nir_tex_flags flags = {
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.lod_mode = lod_mode,
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.offset_mode = offset_mode,
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.has_z_cmpr = tex->is_shadow,
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};
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STATIC_ASSERT(sizeof(flags) == sizeof(tex->backend_flags));
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memcpy(&tex->backend_flags, &flags, sizeof(flags));
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if (tex->op == nir_texop_lod) {
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b->cursor = nir_after_instr(&tex->instr);
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/* The outputs are flipped compared to what NIR expects */
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nir_def *abs = nir_channel(b, &tex->def, 1);
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nir_def *rel = nir_channel(b, &tex->def, 0);
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/* The returned values are not quite what we want:
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* (a) convert from s16/u16 to f32
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* (b) multiply by 1/256
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*
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* TODO: We can make this cheaper once we have 16-bit in NAK
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*/
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abs = nir_u2f32(b, nir_iand_imm(b, abs, 0xffff));
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nir_def *shift = nir_imm_int(b, 16);
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rel = nir_i2f32(b, nir_ishr(b, nir_ishl(b, rel, shift), shift));
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abs = nir_fmul_imm(b, abs, 1.0 / 256.0);
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rel = nir_fmul_imm(b, rel, 1.0 / 256.0);
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nir_def *res = nir_vec2(b, abs, rel);
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nir_def_rewrite_uses_after(&tex->def, res, res->parent_instr);
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}
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return true;
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}
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static bool
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lower_txq(nir_builder *b, nir_tex_instr *tex, const struct nak_compiler *nak)
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{
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b->cursor = nir_before_instr(&tex->instr);
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nir_def *tex_h = NULL, *lod = NULL;
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for (unsigned i = 0; i < tex->num_srcs; i++) {
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switch (tex->src[i].src_type) {
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case nir_tex_src_texture_handle: tex_h = tex->src[i].src.ssa; break;
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case nir_tex_src_sampler_handle: break; /* Ignored */
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case nir_tex_src_lod: lod = tex->src[i].src.ssa; break;
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default:
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unreachable("Unsupported texture source");
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}
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}
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/* TODO: We should only support 32-bit handles */
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tex_h = nir_u2u32(b, tex_h);
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nir_def *txq_src;
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nir_component_mask_t mask;
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switch (tex->op) {
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case nir_texop_txs:
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tex->op = nir_texop_hdr_dim_nv;
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if (lod == NULL)
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lod = nir_imm_int(b, 0);
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txq_src = nir_vec2(b, tex_h, lod);
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mask = BITSET_MASK(tex->def.num_components);
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break;
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case nir_texop_query_levels:
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tex->op = nir_texop_hdr_dim_nv;
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txq_src = nir_vec2(b, tex_h, nir_imm_int(b, 0));
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mask = BITSET_BIT(3);
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break;
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case nir_texop_texture_samples:
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tex->op = nir_texop_tex_type_nv;
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txq_src = tex_h;
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mask = BITSET_BIT(2);
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break;
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default:
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unreachable("Invalid texture query op");
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}
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tex->src[0].src_type = nir_tex_src_backend1;
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nir_src_rewrite(&tex->src[0].src, txq_src);
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/* Remove any extras */
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while (tex->num_srcs > 1)
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nir_tex_instr_remove_src(tex, tex->num_srcs - 1);
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b->cursor = nir_after_instr(&tex->instr);
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/* Only pick off slected components */
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tex->def.num_components = 4;
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nir_def *res = nir_channels(b, &tex->def, mask);
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nir_def_rewrite_uses_after(&tex->def, res, res->parent_instr);
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return true;
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}
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static bool
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lower_tex_instr(nir_builder *b, nir_instr *instr, void *_data)
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{
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const struct nak_compiler *nak = _data;
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if (instr->type != nir_instr_type_tex)
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return false;
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nir_tex_instr *tex = nir_instr_as_tex(instr);
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switch (tex->op) {
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case nir_texop_tex:
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case nir_texop_txb:
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case nir_texop_txl:
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case nir_texop_txd:
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case nir_texop_txf:
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case nir_texop_txf_ms:
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case nir_texop_tg4:
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case nir_texop_lod:
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return lower_tex(b, tex, nak);
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case nir_texop_txs:
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case nir_texop_query_levels:
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case nir_texop_texture_samples:
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return lower_txq(b, tex, nak);
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default:
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unreachable("Unsupported texture instruction");
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}
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}
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bool
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nak_nir_lower_tex(nir_shader *nir, const struct nak_compiler *nak)
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{
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return nir_shader_instructions_pass(nir, lower_tex_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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(void *)nak);
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}
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@ -28,6 +28,30 @@ struct nak_io_addr_offset {
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struct nak_io_addr_offset
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nak_get_io_addr_offset(nir_def *addr, uint8_t imm_bits);
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enum nak_nir_lod_mode {
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NAK_NIR_LOD_MODE_AUTO = 0,
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NAK_NIR_LOD_MODE_ZERO,
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NAK_NIR_LOD_MODE_BIAS,
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NAK_NIR_LOD_MODE_LOD,
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NAK_NIR_LOD_MODE_CLAMP,
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NAK_NIR_LOD_MODE_BIAS_CLAMP,
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};
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enum nak_nir_offset_mode {
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NAK_NIR_OFFSET_MODE_NONE = 0,
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NAK_NIR_OFFSET_MODE_AOFFI,
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NAK_NIR_OFFSET_MODE_PER_PX,
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};
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struct nak_nir_tex_flags {
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enum nak_nir_lod_mode lod_mode:3;
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enum nak_nir_offset_mode offset_mode:2;
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bool has_z_cmpr:1;
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uint32_t pad:26;
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};
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bool nak_nir_lower_tex(nir_shader *nir, const struct nak_compiler *nak);
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#ifdef __cplusplus
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}
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#endif
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