diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index 2d3a8c25b0a..6362cba2031 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -1020,7 +1020,7 @@ a730_raw_magic_regs = [ [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000], [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000], - [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000], + [A6XXRegs.REG_A7XX_GRAS_ROTATION_CNTL, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000], @@ -1075,7 +1075,7 @@ a740_raw_magic_regs = [ [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000], [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000], - [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000], + [A6XXRegs.REG_A7XX_GRAS_ROTATION_CNTL, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000], @@ -1176,7 +1176,7 @@ add_gpus([ [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000], [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000], - [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000], + [A6XXRegs.REG_A7XX_GRAS_ROTATION_CNTL, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000], @@ -1248,7 +1248,7 @@ add_gpus([ [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000], [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000], - [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000], + [A6XXRegs.REG_A7XX_GRAS_ROTATION_CNTL, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000], @@ -1345,7 +1345,7 @@ add_gpus([ [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6, 0x00000000], [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE6+1, 0x00000000], - [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80A7, 0x00000000], + [A6XXRegs.REG_A7XX_GRAS_ROTATION_CNTL, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000], [A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000], diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index 417568e89c6..087702f1227 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -814,7 +814,7 @@ by a particular renderpass/blit. - + @@ -826,18 +826,20 @@ by a particular renderpass/blit. - + + + - - - - + + + + - + @@ -848,17 +850,22 @@ by a particular renderpass/blit. - - + + + + + - + + + - + @@ -877,7 +884,9 @@ by a particular renderpass/blit. - + + + @@ -903,7 +912,7 @@ by a particular renderpass/blit. - + @@ -911,12 +920,13 @@ by a particular renderpass/blit. - + + - + @@ -926,39 +936,66 @@ by a particular renderpass/blit. - - - - - + + + + + + + - - + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - + + + + + + + - + - + + + + @@ -968,7 +1005,10 @@ by a particular renderpass/blit. - + + + + @@ -978,10 +1018,13 @@ by a particular renderpass/blit. - - - - + + + + + + + @@ -1029,7 +1072,7 @@ by a particular renderpass/blit. - + @@ -1039,7 +1082,9 @@ by a particular renderpass/blit. - + + + @@ -1076,17 +1121,22 @@ by a particular renderpass/blit. - + - + - - + + + + + - + + + @@ -1104,30 +1154,35 @@ by a particular renderpass/blit. - - - + + + - + - - + + + + + - - - - - + + - - + + + + + + + @@ -1137,7 +1192,7 @@ by a particular renderpass/blit. - + @@ -1145,20 +1200,32 @@ by a particular renderpass/blit. - - + + + + + - - + + + + + - - - + + + + + + + - + + + @@ -1166,7 +1233,7 @@ by a particular renderpass/blit. - + LRZ write also disabled for blend/etc. @@ -1193,26 +1260,36 @@ by a particular renderpass/blit. - + + + - + - + - + + + - - - + + + + + + + - + + + - @@ -1270,15 +1346,17 @@ by a particular renderpass/blit. - + - + - + - + + + LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values. @@ -1313,23 +1391,22 @@ by a particular renderpass/blit. - + - - - - - - + + + + + + - - - + + @@ -1371,9 +1448,6 @@ by a particular renderpass/blit. - - - @@ -1540,9 +1614,7 @@ by a particular renderpass/blit. - - - + @@ -1556,14 +1628,9 @@ by a particular renderpass/blit. - - - + - - - - + @@ -1599,9 +1666,7 @@ by a particular renderpass/blit. - - - + @@ -1640,8 +1705,9 @@ by a particular renderpass/blit. - - + + + @@ -1650,7 +1716,7 @@ by a particular renderpass/blit. - + @@ -1944,13 +2010,13 @@ by a particular renderpass/blit. - - - + + + - - - + + + @@ -1958,23 +2024,33 @@ by a particular renderpass/blit. - - - + + + - - - + + + + + + + + + + + + + + + - - - + @@ -2014,10 +2090,10 @@ by a particular renderpass/blit. - - - - + + + + @@ -2034,11 +2110,11 @@ by a particular renderpass/blit. - + Packed array of a6xx_varying_interp_mode - + Packed array of a6xx_varying_ps_repl_mode @@ -2047,12 +2123,12 @@ by a particular renderpass/blit. - + - + - - - + + + + + - + - + + - + + + @@ -2100,12 +2181,13 @@ by a particular renderpass/blit. - + - - - - + + + + + @@ -2124,11 +2206,12 @@ by a particular renderpass/blit. - - - - + + + + + @@ -2145,9 +2228,11 @@ by a particular renderpass/blit. ViewID through the VS. - + - + + + @@ -2156,26 +2241,30 @@ by a particular renderpass/blit. - - + + + + + - - - - - - - - - - - - - + + + + + + + + + + + + + + @@ -2189,52 +2278,62 @@ by a particular renderpass/blit. - + - - + - + - + + + - + - - + + + + + - + - + + + + + + + - - - + - + - - + + + - + - + - - - + + - + - + + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + - + - + - + @@ -2296,18 +2371,18 @@ by a particular renderpass/blit. + - - - - - + + + + - + @@ -2316,9 +2391,9 @@ by a particular renderpass/blit. - + - + @@ -2329,34 +2404,39 @@ by a particular renderpass/blit. - - - - - + + + - + + + + Possibly not really "initiating" the draw but the layout is similar to VGT_DRAW_INITIATOR on older gens - - + + - + - - - + - + + + + + Written by CP_SET_VISIBILITY_OVERRIDE handler - + + + @@ -3047,7 +3127,7 @@ by a particular renderpass/blit. UAV state for compute shader: --> - + @@ -3130,9 +3210,9 @@ by a particular renderpass/blit. instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. --> - + - + @@ -3223,7 +3303,7 @@ by a particular renderpass/blit. - + @@ -3263,12 +3343,12 @@ by a particular renderpass/blit. - + - + @@ -3669,7 +3749,7 @@ by a particular renderpass/blit. - + diff --git a/src/freedreno/registers/adreno/adreno_pm4.xml b/src/freedreno/registers/adreno/adreno_pm4.xml index 21ac125fe67..22175f13d1b 100644 --- a/src/freedreno/registers/adreno/adreno_pm4.xml +++ b/src/freedreno/registers/adreno/adreno_pm4.xml @@ -1092,7 +1092,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + + diff --git a/src/freedreno/tests/reference/crash.log b/src/freedreno/tests/reference/crash.log index 752dbd78fc2..ccc3bbe7443 100644 --- a/src/freedreno/tests/reference/crash.log +++ b/src/freedreno/tests/reference/crash.log @@ -5365,7 +5365,7 @@ clusters: 00000000 GRAS_SC_MSAA_SAMPLE_POS_CNTL: { 0 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } - 00000000 GRAS_UNKNOWN_80AF: FALSE + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } 8c629e81 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 40577 | Y = 35938 } fdee19a0 GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 6560 | Y = 65006 } 8867136c GRAS_SC_SCREEN_SCISSOR[0x1].TL: { X = 4972 | Y = 34919 } @@ -5439,7 +5439,7 @@ clusters: 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 00000000 GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } - 00000000 GRAS_UNKNOWN_8110: 0 + 00000000 GRAS_MODE_CNTL: 0 00000000 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED } 00000000 GRAS_A2D_SRC_XMIN: 0 00000000 GRAS_A2D_SRC_XMAX: 0 @@ -5608,7 +5608,7 @@ clusters: 00000000 GRAS_SC_MSAA_SAMPLE_POS_CNTL: { 0 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } - 00000000 GRAS_UNKNOWN_80AF: FALSE + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } 8c629e81 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 40577 | Y = 35938 } fdee19a0 GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 6560 | Y = 65006 } 8867136c GRAS_SC_SCREEN_SCISSOR[0x1].TL: { X = 4972 | Y = 34919 } @@ -5682,7 +5682,7 @@ clusters: 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 00000000 GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } - 00000000 GRAS_UNKNOWN_8110: 0 + 00000000 GRAS_MODE_CNTL: 0 00000000 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_UNORM8 | RASTER_MODE = TYPE_TILED } 00000000 GRAS_A2D_SRC_XMIN: 0 00000000 GRAS_A2D_SRC_XMAX: 0 @@ -6150,7 +6150,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 00000000 VPC_SO[0x3].FLUSH_BASE: 0 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0001 VPC_VS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -6203,7 +6203,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 00000000 VPC_SO[0x3].FLUSH_BASE: 0 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0001 VPC_VS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -6212,7 +6212,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 VPC_SO_OVERRIDE: { 0 } - cluster-name: CLUSTER_FE - context: 0 - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0001 VPC_VS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -6440,7 +6440,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000400 VFD_DEST_CNTL[0x1f].INSTR: { WRITEMASK = 0 | REGID = r16.x } 00000001 VFD_POWER_CNTL: 0x1 - context: 1 - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0001 VPC_VS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -6678,7 +6678,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 0000ffff VPC_DS_SIV_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 00000000 VPC_UNKNOWN_9107: { 0 } 00000003 VPC_RAST_CNTL: { MODE = POLYMODE6_TRIANGLES } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0001 VPC_VS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -6705,7 +6705,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 0000ffff VPC_DS_SIV_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 00000000 VPC_UNKNOWN_9107: { 0 } 00000003 VPC_RAST_CNTL: { MODE = POLYMODE6_TRIANGLES } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0001 VPC_VS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } diff --git a/src/freedreno/tests/reference/crash_prefetch.log b/src/freedreno/tests/reference/crash_prefetch.log index 8eb7a422169..dee34d9e6f5 100644 --- a/src/freedreno/tests/reference/crash_prefetch.log +++ b/src/freedreno/tests/reference/crash_prefetch.log @@ -1934,8 +1934,8 @@ got cmdszdw=38 !+ 00000001 UCHE_UNKNOWN_0E12: 0x1 !+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 } + 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = NO_SHIFT } - + 00000000 GRAS_UNKNOWN_80AF: FALSE - + 00000000 GRAS_UNKNOWN_8110: 0 + + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } + + 00000000 GRAS_MODE_CNTL: 0 !+ 04f06080 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_16_16_16_16_UNORM | MASK = 0xf | IFMT = R2D_FLOAT32 | RASTER_MODE = TYPE_TILED } + 00000000 GRAS_A2D_DEST_TL: { X = 0 | Y = 0 } !+ 0040003e GRAS_A2D_DEST_BR: { X = 62 | Y = 64 } @@ -1968,7 +1968,7 @@ got cmdszdw=38 + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 + 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - + 00000000 VPC_UNKNOWN_9300: 0 + + 00000000 VPC_ROTATION_CNTL: 0 !+ 00000001 VPC_SO_OVERRIDE: { DISABLE } + 00000000 VPC_DBG_ECO_CNTL: 0 + 00000000 VPC_UNKNOWN_9602: FALSE @@ -2236,13 +2236,13 @@ got cmdszdw=38 + 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 } + 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = NO_SHIFT } !+ 00e00000 GRAS_SC_BIN_CNTL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | FORCE_LRZ_WRITE_DIS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } - + 00000000 GRAS_UNKNOWN_80AF: FALSE + + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 0040003e GRAS_SC_WINDOW_SCISSOR_BR: { X = 62 | Y = 64 } + 00000000 GRAS_LRZ_BUFFER_BASE: 0 + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 - + 00000000 GRAS_UNKNOWN_8110: 0 + + 00000000 GRAS_MODE_CNTL: 0 + 00000000 GRAS_A2D_SCISSOR_TL: { X = 0 | Y = 0 } !+ 0040003e GRAS_A2D_SCISSOR_BR: { X = 62 | Y = 64 } + 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS } @@ -2277,7 +2277,7 @@ got cmdszdw=38 + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 + 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - + 00000000 VPC_UNKNOWN_9300: 0 + + 00000000 VPC_ROTATION_CNTL: 0 + 00000001 VPC_SO_OVERRIDE: { DISABLE } + 00000000 VPC_DBG_ECO_CNTL: 0 + 00000000 VPC_UNKNOWN_9602: FALSE @@ -5003,8 +5003,8 @@ ESTIMATED CRASH LOCATION! + 00000001 UCHE_UNKNOWN_0E12: 0x1 + 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 } + 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = NO_SHIFT } - + 00000000 GRAS_UNKNOWN_80AF: FALSE - + 00000000 GRAS_UNKNOWN_8110: 0 + + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } + + 00000000 GRAS_MODE_CNTL: 0 !+ 04f06000 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = FMT6_16_16_16_16_UNORM | MASK = 0xf | IFMT = R2D_FLOAT32 | RASTER_MODE = TYPE_TILED } + 00000000 GRAS_A2D_SRC_XMIN: 0 !+ 00003e00 GRAS_A2D_SRC_XMAX: 62 @@ -5035,7 +5035,7 @@ ESTIMATED CRASH LOCATION! + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 + 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - + 00000000 VPC_UNKNOWN_9300: 0 + + 00000000 VPC_ROTATION_CNTL: 0 + 00000001 VPC_SO_OVERRIDE: { DISABLE } + 00000000 VPC_DBG_ECO_CNTL: 0 + 00000000 VPC_UNKNOWN_9602: FALSE @@ -17016,7 +17016,7 @@ clusters: 00000000 GRAS_SC_MSAA_SAMPLE_POS_CNTL: { 0 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } - 00000000 GRAS_UNKNOWN_80AF: FALSE + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } 0000000a GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 10 | Y = 0 } 0014001e GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 30 | Y = 20 } 200a0a80 GRAS_SC_SCREEN_SCISSOR[0x1].TL: { X = 2688 | Y = 8202 } @@ -17090,7 +17090,7 @@ clusters: 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 00000000 GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } - 00000000 GRAS_UNKNOWN_8110: 0 + 00000000 GRAS_MODE_CNTL: 0 04f06180 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_16_16_16_16_SNORM | MASK = 0xf | IFMT = R2D_FLOAT32 | RASTER_MODE = TYPE_TILED } 00000000 GRAS_A2D_SRC_XMIN: 0 00000000 GRAS_A2D_SRC_XMAX: 0 @@ -17259,7 +17259,7 @@ clusters: 00000000 GRAS_SC_MSAA_SAMPLE_POS_CNTL: { 0 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } - 00000000 GRAS_UNKNOWN_80AF: FALSE + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } 0000000a GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 10 | Y = 0 } 0014001e GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 30 | Y = 20 } 200a0a80 GRAS_SC_SCREEN_SCISSOR[0x1].TL: { X = 2688 | Y = 8202 } @@ -17333,7 +17333,7 @@ clusters: 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 00000000 GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } - 00000000 GRAS_UNKNOWN_8110: 0 + 00000000 GRAS_MODE_CNTL: 0 04f06180 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_16_16_16_16_SNORM | MASK = 0xf | IFMT = R2D_FLOAT32 | RASTER_MODE = TYPE_TILED } 00000000 GRAS_A2D_SRC_XMIN: 0 00000000 GRAS_A2D_SRC_XMAX: 0 @@ -17801,7 +17801,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 00000000 VPC_SO[0x3].FLUSH_BASE: 0 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0004 VPC_VS_CNTL: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -17854,7 +17854,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 00000000 VPC_SO[0x3].FLUSH_BASE: 0 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0004 VPC_VS_CNTL: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -17863,7 +17863,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000001 VPC_SO_OVERRIDE: { DISABLE } - cluster-name: CLUSTER_FE - context: 0 - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0004 VPC_VS_CNTL: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -18091,7 +18091,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000220 VFD_DEST_CNTL[0x1f].INSTR: { WRITEMASK = 0 | REGID = r8.z } 00000001 VFD_POWER_CNTL: 0x1 - context: 1 - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0004 VPC_VS_CNTL: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -18329,7 +18329,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 0000ffff VPC_DS_SIV_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 00000000 VPC_UNKNOWN_9107: { 0 } 00000003 VPC_RAST_CNTL: { MODE = POLYMODE6_TRIANGLES } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0004 VPC_VS_CNTL: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -18356,7 +18356,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 0000ffff VPC_DS_SIV_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 00000000 VPC_UNKNOWN_9107: { 0 } 00000003 VPC_RAST_CNTL: { MODE = POLYMODE6_TRIANGLES } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0004 VPC_VS_CNTL: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } diff --git a/src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log index 8c158b2fcc0..1b6a9b9d661 100644 --- a/src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log +++ b/src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log @@ -89,8 +89,8 @@ cmdstream[0]: 265 dwords write RB_SRGB_CNTL (880f) RB_SRGB_CNTL: { 0 } 00000000010580dc: 0000: 48880f01 00000000 - write GRAS_UNKNOWN_8110 (8110) - GRAS_UNKNOWN_8110: 0 + write GRAS_MODE_CNTL (8110) + GRAS_MODE_CNTL: 0 00000000010580e4: 0000: 40811001 00000000 write RB_INTERP_CNTL (8809) RB_INTERP_CNTL: { IJ_PERSP_PIXEL | COORD_MASK = 0 | UNK10 } @@ -131,8 +131,8 @@ cmdstream[0]: 265 dwords write VPC_REPLACE_MODE_CNTL (9236) VPC_REPLACE_MODE_CNTL: { 0 } 000000000105814c: 0000: 40923601 00000000 - write VPC_UNKNOWN_9300 (9300) - VPC_UNKNOWN_9300: 0 + write VPC_ROTATION_CNTL (9300) + VPC_ROTATION_CNTL: 0 0000000001058154: 0000: 48930001 00000000 write VPC_SO_OVERRIDE (9306) VPC_SO_OVERRIDE: { DISABLE } @@ -158,8 +158,8 @@ cmdstream[0]: 265 dwords write GRAS_SC_CNTL (80a0) GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } 0000000001058194: 0000: 4080a001 00000002 - write GRAS_UNKNOWN_80AF (80af) - GRAS_UNKNOWN_80AF: FALSE + write GRAS_SC_SCREEN_SCISSOR_CNTL (80af) + GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } 000000000105819c: 0000: 4080af01 00000000 write VPC_UNKNOWN_9210 (9210) VPC_UNKNOWN_9210: 0 @@ -274,9 +274,9 @@ cmdstream[0]: 265 dwords !+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 } + 00000000 GRAS_SU_CONSERVATIVE_RAS_CNTL: { SHIFTAMOUNT = NO_SHIFT } !+ 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } - + 00000000 GRAS_UNKNOWN_80AF: FALSE + + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } + 00000000 GRAS_LRZ_CNTL: { DIR = 0 } - + 00000000 GRAS_UNKNOWN_8110: 0 + + 00000000 GRAS_MODE_CNTL: 0 !+ 10f03080 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | UNK28 | RASTER_MODE = TYPE_TILED } + 00000000 GRAS_A2D_DEST_TL: { X = 0 | Y = 0 } !+ 00ff00ff GRAS_A2D_DEST_BR: { X = 255 | Y = 255 } @@ -313,7 +313,7 @@ cmdstream[0]: 265 dwords + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 + 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - + 00000000 VPC_UNKNOWN_9300: 0 + + 00000000 VPC_ROTATION_CNTL: 0 !+ 00000001 VPC_SO_OVERRIDE: { DISABLE } + 00000000 VPC_DBG_ECO_CNTL: 0 + 00000000 VPC_UNKNOWN_9602: FALSE diff --git a/src/freedreno/tests/reference/fd-clouds.log b/src/freedreno/tests/reference/fd-clouds.log index 1ca98204064..86921b000e8 100644 --- a/src/freedreno/tests/reference/fd-clouds.log +++ b/src/freedreno/tests/reference/fd-clouds.log @@ -86,8 +86,8 @@ cmdstream[0]: 1023 dwords write GRAS_LRZ_PS_SAMPLEFREQ_CNTL (8109) GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } 0000000001d910d4: 0000: 48810901 00000000 - write GRAS_UNKNOWN_8110 (8110) - GRAS_UNKNOWN_8110: 0x2 + write GRAS_MODE_CNTL (8110) + GRAS_MODE_CNTL: 0x2 0000000001d910dc: 0000: 40811001 00000002 write RB_UNKNOWN_8818 (8818) RB_UNKNOWN_8818: 0 @@ -116,8 +116,8 @@ cmdstream[0]: 1023 dwords write VPC_REPLACE_MODE_CNTL (9236) VPC_REPLACE_MODE_CNTL: { 0 } 0000000001d91124: 0000: 40923601 00000000 - write VPC_UNKNOWN_9300 (9300) - VPC_UNKNOWN_9300: 0 + write VPC_ROTATION_CNTL (9300) + VPC_ROTATION_CNTL: 0 0000000001d9112c: 0000: 48930001 00000000 write VPC_SO_OVERRIDE (9306) VPC_SO_OVERRIDE: { DISABLE } @@ -149,8 +149,8 @@ cmdstream[0]: 1023 dwords write GRAS_SC_CNTL (80a0) GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } 0000000001d9117c: 0000: 4080a001 00000002 - write GRAS_UNKNOWN_80AF (80af) - GRAS_UNKNOWN_80AF: FALSE + write GRAS_SC_SCREEN_SCISSOR_CNTL (80af) + GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } 0000000001d91184: 0000: 4080af01 00000000 write VPC_UNKNOWN_9210 (9210) VPC_UNKNOWN_9210: 0 @@ -924,7 +924,7 @@ cmdstream[0]: 1023 dwords + 00000000 GRAS_SC_MSAA_SAMPLE_POS_CNTL: { 0 } + 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } + 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } - + 00000000 GRAS_UNKNOWN_80AF: FALSE + + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } + 00000000 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } !+ 059f086f GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 2159 | Y = 1439 } + 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 } @@ -937,7 +937,7 @@ cmdstream[0]: 1023 dwords + 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 + 00000000 GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } -!+ 00000002 GRAS_UNKNOWN_8110: 0x2 +!+ 00000002 GRAS_MODE_CNTL: 0x2 + 00000000 GRAS_A2D_SCISSOR_TL: { X = 0 | Y = 0 } !+ 059f086f GRAS_A2D_SCISSOR_BR: { X = 2159 | Y = 1439 } !+ 00000880 GRAS_DBG_ECO_CNTL: { UNK7 | LRZCACHELOCKDIS } @@ -1007,7 +1007,7 @@ cmdstream[0]: 1023 dwords !+ ffffffff VPC_VARYING_LM_TRANSFER_CNTL[0x2].DISABLE: 0xffffffff !+ ffffffff VPC_VARYING_LM_TRANSFER_CNTL[0x3].DISABLE: 0xffffffff + 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - + 00000000 VPC_UNKNOWN_9300: 0 + + 00000000 VPC_ROTATION_CNTL: 0 !+ 00ff0004 VPC_VS_CNTL: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } !+ ff00ff00 VPC_PS_CNTL: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } + 00000000 VPC_SO_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } diff --git a/src/freedreno/tests/reference/prefetch-test.log b/src/freedreno/tests/reference/prefetch-test.log index c942e1d0dfe..7a46fa74f63 100644 --- a/src/freedreno/tests/reference/prefetch-test.log +++ b/src/freedreno/tests/reference/prefetch-test.log @@ -2502,13 +2502,13 @@ got cmdszdw=416 !+ 00000002 GRAS_SC_CNTL: { CCUSINGLECACHELINESIZE = 0x2 | SINGLE_PRIM_MODE = NO_FLUSH | RASTER_MODE = TYPE_TILED | RASTER_DIRECTION = LR_TB | SEQUENCED_THREAD_DISTRIBUTION = DIST_SCREEN_COORD | ROTATION = 0 } !+ 00c00000 GRAS_SC_BIN_CNTL: { BINW = 0 | BINH = 0 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_SYSMEM | LRZ_FEEDBACK_ZMODE_MASK = LRZ_FEEDBACK_NONE } + 00000000 GRAS_SC_MSAA_SAMPLE_POS_CNTL: { 0 } - + 00000000 GRAS_UNKNOWN_80AF: FALSE + + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } + 00000000 GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_SC_WINDOW_SCISSOR_BR: { X = 63 | Y = 63 } + 00000000 GRAS_LRZ_CNTL: { DIR = 0 } + 00000000 GRAS_LRZ_PS_INPUT_CNTL: { FRAGCOORDSAMPLEMODE = FRAGCOORD_CENTER } + 00000000 GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } -!+ 00000002 GRAS_UNKNOWN_8110: 0x2 +!+ 00000002 GRAS_MODE_CNTL: 0x2 !+ 10f03080 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | UNK28 | RASTER_MODE = TYPE_TILED } + 00000000 GRAS_A2D_DEST_TL: { X = 0 | Y = 0 } !+ 003f003f GRAS_A2D_DEST_BR: { X = 63 | Y = 63 } @@ -2553,7 +2553,7 @@ got cmdszdw=416 + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 + 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - + 00000000 VPC_UNKNOWN_9300: 0 + + 00000000 VPC_ROTATION_CNTL: 0 + 00000000 VPC_SO_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } !+ 00000001 VPC_SO_OVERRIDE: { DISABLE } + 00000000 VPC_DBG_ECO_CNTL: 0 @@ -142907,7 +142907,7 @@ clusters: 00000000 GRAS_SC_MSAA_SAMPLE_POS_CNTL: { 0 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } - 00000000 GRAS_UNKNOWN_80AF: FALSE + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } 00000000 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } 003f003f GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 63 | Y = 63 } 089031b8 GRAS_SC_SCREEN_SCISSOR[0x1].TL: { X = 12728 | Y = 2192 } @@ -142981,7 +142981,7 @@ clusters: 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 00000000 GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } - 00000002 GRAS_UNKNOWN_8110: 0x2 + 00000002 GRAS_MODE_CNTL: 0x2 10f03080 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | UNK28 | RASTER_MODE = TYPE_TILED } 00000000 GRAS_A2D_SRC_XMIN: 0 00000000 GRAS_A2D_SRC_XMAX: 0 @@ -143150,7 +143150,7 @@ clusters: 00000000 GRAS_SC_MSAA_SAMPLE_POS_CNTL: { 0 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } 00000000 GRAS_SC_PROGRAMMABLE_MSAA_POS_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 } - 00000000 GRAS_UNKNOWN_80AF: FALSE + 00000000 GRAS_SC_SCREEN_SCISSOR_CNTL: { 0 } 00000000 GRAS_SC_SCREEN_SCISSOR[0].TL: { X = 0 | Y = 0 } 003f003f GRAS_SC_SCREEN_SCISSOR[0].BR: { X = 63 | Y = 63 } 089031b8 GRAS_SC_SCREEN_SCISSOR[0x1].TL: { X = 12728 | Y = 2192 } @@ -143224,7 +143224,7 @@ clusters: 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 } 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0 00000000 GRAS_LRZ_PS_SAMPLEFREQ_CNTL: { 0 } - 00000002 GRAS_UNKNOWN_8110: 0x2 + 00000002 GRAS_MODE_CNTL: 0x2 10f03080 GRAS_A2D_BLT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 | UNK28 | RASTER_MODE = TYPE_TILED } 00000000 GRAS_A2D_SRC_XMIN: 0 00000000 GRAS_A2D_SRC_XMAX: 0 @@ -143692,7 +143692,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 00000000 VPC_SO[0x3].FLUSH_BASE: 0 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0206 VPC_VS_CNTL: { STRIDE_IN_VPC = 6 | POSITIONLOC = 2 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -143745,7 +143745,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 VPC_SO[0x3].BUFFER_OFFSET: 0 00000000 VPC_SO[0x3].FLUSH_BASE: 0 00000000 VPC_REPLACE_MODE_CNTL: { 0 } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0206 VPC_VS_CNTL: { STRIDE_IN_VPC = 6 | POSITIONLOC = 2 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -143754,7 +143754,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000000 VPC_SO_OVERRIDE: { 0 } - cluster-name: CLUSTER_FE - context: 0 - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0206 VPC_VS_CNTL: { STRIDE_IN_VPC = 6 | POSITIONLOC = 2 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -143982,7 +143982,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 00000402 VFD_DEST_CNTL[0x1f].INSTR: { WRITEMASK = 0x2 | REGID = r16.x } 00000000 VFD_POWER_CNTL: 0 - context: 1 - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0206 VPC_VS_CNTL: { STRIDE_IN_VPC = 6 | POSITIONLOC = 2 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -144220,7 +144220,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 0000ffff VPC_DS_SIV_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 00000000 VPC_UNKNOWN_9107: { 0 } 00000003 VPC_RAST_CNTL: { MODE = POLYMODE6_TRIANGLES } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0206 VPC_VS_CNTL: { STRIDE_IN_VPC = 6 | POSITIONLOC = 2 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } @@ -144247,7 +144247,7 @@ WARNING: 64b discontinuity (no _LO dword for 890d) 0000ffff VPC_DS_SIV_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 00000000 VPC_UNKNOWN_9107: { 0 } 00000003 VPC_RAST_CNTL: { MODE = POLYMODE6_TRIANGLES } - 00000000 VPC_UNKNOWN_9300: 0 + 00000000 VPC_ROTATION_CNTL: 0 00ff0206 VPC_VS_CNTL: { STRIDE_IN_VPC = 6 | POSITIONLOC = 2 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_CNTL: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc index 62328016b2d..d908e698986 100644 --- a/src/freedreno/vulkan/tu_clear_blit.cc +++ b/src/freedreno/vulkan/tu_clear_blit.cc @@ -881,7 +881,7 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type, tu6_emit_vpc(cs, vs, NULL, NULL, NULL, fs); if (CHIP >= A7XX) { - tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2)); + tu_cs_emit_regs(cs, A6XX_GRAS_MODE_CNTL(0x2)); tu_cs_emit_regs(cs, A7XX_SP_RENDER_CNTL(.fs_disable = false)); } @@ -902,7 +902,7 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type, .vp_clip_code_ignore = 1, .vp_xform_disable = 1, .persp_division_disable = 1,)); - tu_cs_emit_regs(cs, A6XX_GRAS_SU_CNTL()); // XXX msaa enable? + tu_cs_emit_regs(cs, GRAS_SU_CNTL(CHIP)); // XXX msaa enable? tu_cs_emit_regs(cs, VPC_RAST_STREAM_CNTL(CHIP)); if (CHIP == A6XX) { @@ -1592,7 +1592,7 @@ r3d_setup(struct tu_cmd_buffer *cmd, tu_cs_emit_regs(cs, A6XX_RB_VRS_CONFIG()); tu_cs_emit_regs(cs, A7XX_SP_VRS_CONFIG()); - tu_cs_emit_regs(cs, A7XX_GRAS_VRS_CONFIG()); + tu_cs_emit_regs(cs, GRAS_VRS_CONFIG(CHIP)); } tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL, diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 950a874ab9b..a6f3449956f 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -400,17 +400,14 @@ emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem) if (dev->physical_device->info->a7xx.has_gmem_vpc_attr_buf) { tu_cs_emit_regs(cs, - A7XX_VPC_ATTR_BUF_GMEM_SIZE( - .size_gmem = + VPC_ATTR_BUF_GMEM_SIZE(CHIP, gmem ? dev->physical_device->vpc_attr_buf_size_gmem : dev->physical_device->vpc_attr_buf_size_bypass), - A7XX_VPC_ATTR_BUF_GMEM_BASE( - .base_gmem = + VPC_ATTR_BUF_GMEM_BASE(CHIP, gmem ? dev->physical_device->vpc_attr_buf_offset_gmem : dev->physical_device->vpc_attr_buf_offset_bypass), ); tu_cs_emit_regs(cs, A7XX_PC_ATTR_BUF_GMEM_SIZE( - .size_gmem = gmem ? dev->physical_device->vpc_attr_buf_size_gmem : dev->physical_device->vpc_attr_buf_size_bypass), ); } @@ -1765,7 +1762,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs) tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, phys_dev->info->a6xx.magic.PC_MODE_CNTL); - tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_8110, 0); + tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_MODE_CNTL, 0); tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8818, 0); @@ -1781,13 +1778,13 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs) tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0); tu_cs_emit_regs(cs, A6XX_VPC_REPLACE_MODE_CNTL(false)); - tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0); + tu_cs_emit_write_reg(cs, REG_A6XX_VPC_ROTATION_CNTL, 0); tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(true)); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0); - tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_UNKNOWN_80AF, 0); + tu_cs_emit_regs(cs, GRAS_SC_SCREEN_SCISSOR_CNTL(CHIP)); if (CHIP == A6XX) { tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0); tu_cs_emit_regs(cs, A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL()); @@ -1875,7 +1872,7 @@ tu7_emit_tile_render_begin_regs(struct tu_cs *cs) tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0)); - tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2)); + tu_cs_emit_regs(cs, A6XX_GRAS_MODE_CNTL(0x2)); tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4)); tu_cs_emit_regs(cs, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM)); @@ -2565,7 +2562,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs, tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0)); - tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2)); + tu_cs_emit_regs(cs, A6XX_GRAS_MODE_CNTL(0x2)); tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4)); tu_cs_emit_regs(cs, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_SYSMEM)); diff --git a/src/freedreno/vulkan/tu_pipeline.cc b/src/freedreno/vulkan/tu_pipeline.cc index b06f6d3a82f..bfb16340229 100644 --- a/src/freedreno/vulkan/tu_pipeline.cc +++ b/src/freedreno/vulkan/tu_pipeline.cc @@ -2556,9 +2556,8 @@ tu6_emit_viewport(struct tu_cs *cs, tu_cs_emit(cs, fui(MAX2(viewport->minDepth, viewport->maxDepth))); } } - tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ, 1); - tu_cs_emit(cs, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(guardband.width) | - A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(guardband.height)); + tu_cs_emit_regs(cs, + GRAS_CL_GUARDBAND_CLIP_ADJ(CHIP, .horz = guardband.width, .vert = guardband.height)); /* TODO: what to do about this and multi viewport ? */ float z_clamp_min = vp->viewport_count ? MIN2(vp->viewports[0].minDepth, vp->viewports[0].maxDepth) : 0; @@ -3297,7 +3296,7 @@ tu6_emit_rast(struct tu_cs *cs, rs->line.mode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_KHR ? BRESENHAM : RECTANGULAR; tu_cs_emit_regs(cs, - A6XX_GRAS_SU_CNTL( + GRAS_SU_CNTL(CHIP, .cull_front = rs->cull_mode & VK_CULL_MODE_FRONT_BIT, .cull_back = rs->cull_mode & VK_CULL_MODE_BACK_BIT, .front_cw = rs->front_face == VK_FRONT_FACE_CLOCKWISE, @@ -3608,7 +3607,7 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs, if (!fsr || (!fs_reads_fsr && vk_fragment_shading_rate_is_disabled(fsr))) { tu_cs_emit_regs(cs, A6XX_RB_VRS_CONFIG()); tu_cs_emit_regs(cs, A7XX_SP_VRS_CONFIG()); - tu_cs_emit_regs(cs, A7XX_GRAS_VRS_CONFIG()); + tu_cs_emit_regs(cs, GRAS_VRS_CONFIG(CHIP)); return; } @@ -3646,7 +3645,7 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs, .attachment_fsr_enable = enable_att_fsr, .primitive_fsr_enable = enable_prim_fsr)); tu_cs_emit_regs( - cs, A7XX_GRAS_VRS_CONFIG( + cs, GRAS_VRS_CONFIG(CHIP, .pipeline_fsr_enable = enable_draw_fsr, .frag_size_x = util_logbase2(frag_width), .frag_size_y = util_logbase2(frag_height), diff --git a/src/freedreno/vulkan/tu_shader.cc b/src/freedreno/vulkan/tu_shader.cc index 2e1aee87d72..54791b95ff0 100644 --- a/src/freedreno/vulkan/tu_shader.cc +++ b/src/freedreno/vulkan/tu_shader.cc @@ -2177,7 +2177,7 @@ tu6_emit_fs(struct tu_cs *cs, tu_cs_emit_regs(cs, A6XX_PC_PS_CNTL(.primitiveiden = fs && fs->reads_primid)); if (CHIP >= A7XX) { - tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2)); + tu_cs_emit_regs(cs, A6XX_GRAS_MODE_CNTL(0x2)); } if (fs) { diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc index b1353fba735..19967455202 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc @@ -319,7 +319,7 @@ emit_blit_setup(fd_ncrb &ncrb, enum pipe_format pfmt, COND(scissor_enable, A6XX_RB_A2D_BLT_CNTL_SCISSOR); ncrb.add(A6XX_RB_A2D_BLT_CNTL(.dword = blit_cntl)); - ncrb.add(A6XX_GRAS_A2D_BLT_CNTL(.dword = blit_cntl)); + ncrb.add(GRAS_A2D_BLT_CNTL(CHIP, .dword = blit_cntl)); if (CHIP >= A7XX) { ncrb.add(TPL1_A2D_BLT_CNTL(CHIP, @@ -465,13 +465,13 @@ emit_blit_buffer(struct fd_context *ctx, fd_cs &cs, const struct pipe_blit_info */ emit_blit_buffer_dst(ncrb, dst, doff, p, FMT6_8_UNORM); - ncrb.add(A6XX_GRAS_A2D_SRC_XMIN(sshift)); - ncrb.add(A6XX_GRAS_A2D_SRC_XMAX(sshift + w - 1)); - ncrb.add(A6XX_GRAS_A2D_SRC_YMIN(0)); - ncrb.add(A6XX_GRAS_A2D_SRC_YMAX(0)); + ncrb.add(GRAS_A2D_SRC_XMIN(CHIP, sshift)); + ncrb.add(GRAS_A2D_SRC_XMAX(CHIP, sshift + w - 1)); + ncrb.add(GRAS_A2D_SRC_YMIN(CHIP, 0)); + ncrb.add(GRAS_A2D_SRC_YMAX(CHIP, 0)); - ncrb.add(A6XX_GRAS_A2D_DEST_TL(.x = dshift)); - ncrb.add(A6XX_GRAS_A2D_DEST_BR(.x = dshift + w - 1)); + ncrb.add(GRAS_A2D_DEST_TL(CHIP, .x = dshift)); + ncrb.add(GRAS_A2D_DEST_BR(CHIP, .x = dshift + w - 1)); } /* @@ -500,10 +500,10 @@ clear_ubwc_setup(fd_cs &cs) ncrb.add(A6XX_RB_A2D_CLEAR_COLOR_DW2()); ncrb.add(A6XX_RB_A2D_CLEAR_COLOR_DW3()); - ncrb.add(A6XX_GRAS_A2D_SRC_XMIN(0)); - ncrb.add(A6XX_GRAS_A2D_SRC_XMAX(0)); - ncrb.add(A6XX_GRAS_A2D_SRC_YMIN(0)); - ncrb.add(A6XX_GRAS_A2D_SRC_YMAX(0)); + ncrb.add(GRAS_A2D_SRC_XMIN(CHIP, 0)); + ncrb.add(GRAS_A2D_SRC_XMAX(CHIP, 0)); + ncrb.add(GRAS_A2D_SRC_YMIN(CHIP, 0)); + ncrb.add(GRAS_A2D_SRC_YMAX(CHIP, 0)); } template @@ -539,8 +539,8 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt */ emit_blit_buffer_dst(ncrb, rsc, offset, p, FMT6_8_UNORM); - ncrb.add(A6XX_GRAS_A2D_DEST_TL(.x = 0, .y = 0)); - ncrb.add(A6XX_GRAS_A2D_DEST_BR(.x = w - 1, .y = h - 1)); + ncrb.add(GRAS_A2D_DEST_TL(CHIP, .x = 0, .y = 0)); + ncrb.add(GRAS_A2D_DEST_BR(CHIP, .x = w - 1, .y = h - 1)); } /* @@ -690,20 +690,20 @@ emit_blit_texture_setup(fd_cs &cs, const struct pipe_blit_info *info) fd_ncrb ncrb(cs, 13); - ncrb.add(A6XX_GRAS_A2D_SRC_XMIN(MIN2(sx1, sx2))); - ncrb.add(A6XX_GRAS_A2D_SRC_XMAX(MAX2(sx1, sx2) - 1)); - ncrb.add(A6XX_GRAS_A2D_SRC_YMIN(MIN2(sy1, sy2))); - ncrb.add(A6XX_GRAS_A2D_SRC_YMAX(MAX2(sy1, sy2) - 1)); + ncrb.add(GRAS_A2D_SRC_XMIN(CHIP, MIN2(sx1, sx2))); + ncrb.add(GRAS_A2D_SRC_XMAX(CHIP, MAX2(sx1, sx2) - 1)); + ncrb.add(GRAS_A2D_SRC_YMIN(CHIP, MIN2(sy1, sy2))); + ncrb.add(GRAS_A2D_SRC_YMAX(CHIP, MAX2(sy1, sy2) - 1)); - ncrb.add(A6XX_GRAS_A2D_DEST_TL(.x = MIN2(dx1, dx2), .y = MIN2(dy1, dy2))); - ncrb.add(A6XX_GRAS_A2D_DEST_BR(.x = MAX2(dx1, dx2) - 1, .y = MAX2(dy1, dy2) - 1)); + ncrb.add(GRAS_A2D_DEST_TL(CHIP, .x = MIN2(dx1, dx2), .y = MIN2(dy1, dy2))); + ncrb.add(GRAS_A2D_DEST_BR(CHIP, .x = MAX2(dx1, dx2) - 1, .y = MAX2(dy1, dy2) - 1)); if (info->scissor_enable) { - ncrb.add(A6XX_GRAS_A2D_SCISSOR_TL( + ncrb.add(GRAS_A2D_SCISSOR_TL(CHIP, .x = info->scissor.minx, .y = info->scissor.miny, )); - ncrb.add(A6XX_GRAS_A2D_SCISSOR_BR( + ncrb.add(GRAS_A2D_SCISSOR_BR(CHIP, .x = info->scissor.maxx - 1, .y = info->scissor.maxy - 1, )); @@ -805,8 +805,8 @@ clear_lrz_setup(fd_cs &cs, struct fd_resource *zsbuf, struct fd_bo *lrz, double { fd_ncrb ncrb(cs, 15); - ncrb.add(A6XX_GRAS_A2D_DEST_TL(.x = 0, .y = 0)); - ncrb.add(A6XX_GRAS_A2D_DEST_BR( + ncrb.add(GRAS_A2D_DEST_TL(CHIP, .x = 0, .y = 0)); + ncrb.add(GRAS_A2D_DEST_BR(CHIP, .x = zsbuf->lrz_layout.lrz_pitch - 1, .y = zsbuf->lrz_layout.lrz_height - 1, )); @@ -994,8 +994,8 @@ fd6_clear_buffer(struct pipe_context *pctx, with_ncrb (cs, 6) { emit_blit_buffer_dst(ncrb, rsc, doff, 0, fmt); - ncrb.add(A6XX_GRAS_A2D_DEST_TL(.x = dst_x)); - ncrb.add(A6XX_GRAS_A2D_DEST_BR(.x = dst_x + width - 1)); + ncrb.add(GRAS_A2D_DEST_TL(CHIP, .x = dst_x)); + ncrb.add(GRAS_A2D_DEST_BR(CHIP, .x = dst_x + width - 1)); } emit_blit_fini(ctx, cs); @@ -1028,11 +1028,11 @@ clear_surface_setup(fd_cs &cs, struct pipe_surface *psurf, uint32_t nr_samples = fd_resource_nr_samples(psurf->texture); fd_ncrb ncrb(cs, 11); - ncrb.add(A6XX_GRAS_A2D_DEST_TL( + ncrb.add(GRAS_A2D_DEST_TL(CHIP, .x = box2d->x * nr_samples, .y = box2d->y, )); - ncrb.add(A6XX_GRAS_A2D_DEST_BR( + ncrb.add(GRAS_A2D_DEST_BR(CHIP, .x = (box2d->x + box2d->width) * nr_samples - 1, .y = box2d->y + box2d->height - 1, )); @@ -1167,13 +1167,13 @@ resolve_tile_setup(struct fd_batch *batch, fd_cs &cs, uint32_t base, unsigned height = pipe_surface_height(psurf); fd_ncrb ncrb(cs, 26); - ncrb.add(A6XX_GRAS_A2D_DEST_TL(.x = 0, .y = 0)); - ncrb.add(A6XX_GRAS_A2D_DEST_BR(.x = width - 1, .y = height - 1)); + ncrb.add(GRAS_A2D_DEST_TL(CHIP, .x = 0, .y = 0)); + ncrb.add(GRAS_A2D_DEST_BR(CHIP, .x = width - 1, .y = height - 1)); - ncrb.add(A6XX_GRAS_A2D_SRC_XMIN(0)); - ncrb.add(A6XX_GRAS_A2D_SRC_XMAX(width - 1)); - ncrb.add(A6XX_GRAS_A2D_SRC_YMIN(0)); - ncrb.add(A6XX_GRAS_A2D_SRC_YMAX(height - 1)); + ncrb.add(GRAS_A2D_SRC_XMIN(CHIP, 0)); + ncrb.add(GRAS_A2D_SRC_XMAX(CHIP, width - 1)); + ncrb.add(GRAS_A2D_SRC_YMIN(CHIP, 0)); + ncrb.add(GRAS_A2D_SRC_YMAX(CHIP, height - 1)); /* Enable scissor bit, which will take into account the window scissor * which is set per-tile diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_context.cc b/src/gallium/drivers/freedreno/a6xx/fd6_context.cc index 25cca6d374b..1258db29c51 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_context.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_context.cc @@ -309,9 +309,9 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv, fd_crb crb(fd6_ctx->base.pipe, 3); - crb.add(A6XX_GRAS_SC_MSAA_SAMPLE_POS_CNTL()) + crb.add(GRAS_SC_MSAA_SAMPLE_POS_CNTL(CHIP)) .add(A6XX_RB_MSAA_SAMPLE_POS_CNTL()) - .add(A6XX_TPL1_MSAA_SAMPLE_POS_CNTL()); + .add(TPL1_MSAA_SAMPLE_POS_CNTL(CHIP)); fd6_ctx->sample_locations_disable_stateobj = crb.ring(); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.cc b/src/gallium/drivers/freedreno/a6xx/fd6_draw.cc index 0a4f8f1c77f..f07ab5a2dab 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.cc @@ -457,7 +457,7 @@ draw_vbos(struct fd_context *ctx, const struct pipe_draw_info *info, uint32_t restart_index = info->primitive_restart ? info->restart_index : 0xffffffff; if (ctx->last.dirty || (ctx->last.restart_index != restart_index)) { - crb.add(A6XX_PC_RESTART_INDEX(restart_index)); + crb.add(PC_RESTART_INDEX(CHIP, restart_index)); ctx->last.restart_index = restart_index; } } diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc index a355d970c8a..b4385ced192 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc @@ -228,7 +228,7 @@ build_lrz(struct fd6_emit *emit) assert_dt fd_crb crb(ctx->batch->submit, nregs); if (CHIP >= A7XX) { - crb.add(A6XX_GRAS_LRZ_CNTL( + crb.add(GRAS_LRZ_CNTL(CHIP, .enable = lrz.enable, .lrz_write = lrz.write, .greater = lrz.direction == FD_LRZ_GREATER, @@ -240,7 +240,7 @@ build_lrz(struct fd6_emit *emit) assert_dt .fc_enable = false, )); } else { - crb.add(A6XX_GRAS_LRZ_CNTL( + crb.add(GRAS_LRZ_CNTL(CHIP, .enable = lrz.enable, .lrz_write = lrz.write, .greater = lrz.direction == FD_LRZ_GREATER, @@ -254,11 +254,12 @@ build_lrz(struct fd6_emit *emit) assert_dt crb.add(A6XX_RB_LRZ_CNTL(.enable = lrz.enable, )) .add(A6XX_RB_DEPTH_PLANE_CNTL(.z_mode = lrz.z_mode, )) - .add(A6XX_GRAS_SU_DEPTH_PLANE_CNTL(.z_mode = lrz.z_mode, )); + .add(GRAS_SU_DEPTH_PLANE_CNTL(CHIP, .z_mode = lrz.z_mode, )); return crb.ring(); } +template static struct fd_ringbuffer * build_scissor(struct fd6_emit *emit) assert_dt { @@ -269,8 +270,8 @@ build_scissor(struct fd6_emit *emit) assert_dt fd_crb crb(emit->ctx->batch->submit, 2 * num_viewports); for (unsigned i = 0; i < num_viewports; i++) { - crb.add(A6XX_GRAS_SC_SCREEN_SCISSOR_TL(i, .x = scissors[i].minx, .y = scissors[i].miny)) - .add(A6XX_GRAS_SC_SCREEN_SCISSOR_BR(i, .x = scissors[i].maxx, .y = scissors[i].maxy)); + crb.add(GRAS_SC_SCREEN_SCISSOR_TL(CHIP, i, .x = scissors[i].minx, .y = scissors[i].miny)) + .add(GRAS_SC_SCREEN_SCISSOR_BR(CHIP, i, .x = scissors[i].maxx, .y = scissors[i].maxy)); } return crb.ring(); @@ -341,6 +342,7 @@ build_blend_color(struct fd6_emit *emit) assert_dt .ring(); } +template static struct fd_ringbuffer * build_sample_locations(struct fd6_emit *emit) assert_dt @@ -366,11 +368,11 @@ build_sample_locations(struct fd6_emit *emit) } return fd_crb(ctx->batch->submit, 6) - .add(A6XX_GRAS_SC_MSAA_SAMPLE_POS_CNTL(.location_enable = true)) - .add(A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations)) + .add(GRAS_SC_MSAA_SAMPLE_POS_CNTL(CHIP, .location_enable = true)) + .add(GRAS_SC_PROGRAMMABLE_MSAA_POS_0(CHIP, .dword = sample_locations)) .add(A6XX_RB_MSAA_SAMPLE_POS_CNTL(.location_enable = true)) .add(A6XX_RB_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations)) - .add(A6XX_TPL1_MSAA_SAMPLE_POS_CNTL(.location_enable = true)) + .add(TPL1_MSAA_SAMPLE_POS_CNTL(CHIP, .location_enable = true)) .add(A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations)) .ring(); } @@ -398,8 +400,8 @@ fd6_emit_streamout(fd_cs &cs, struct fd6_emit *emit) assert_dt target->stride = info->stride[i]; fd_pkt4(cs, 3) - .add(A6XX_VPC_SO_BUFFER_BASE(i, fd_resource(target->base.buffer)->bo)) - .add(A6XX_VPC_SO_BUFFER_SIZE(i, target->base.buffer_size + target->base.buffer_offset)); + .add(VPC_SO_BUFFER_BASE(CHIP, i, fd_resource(target->base.buffer)->bo)) + .add(VPC_SO_BUFFER_SIZE(CHIP, i, target->base.buffer_size + target->base.buffer_offset)); struct fd_bo *offset_bo = fd_resource(target->offset_buf)->bo; @@ -411,11 +413,11 @@ fd6_emit_streamout(fd_cs &cs, struct fd6_emit *emit) assert_dt .add(target->base.buffer_offset); fd_pkt4(cs, 1) - .add(A6XX_VPC_SO_BUFFER_OFFSET(i,target->base.buffer_offset)); + .add(VPC_SO_BUFFER_OFFSET(CHIP, i,target->base.buffer_offset)); } else { fd_pkt7(cs, CP_MEM_TO_REG, 3) .add(CP_MEM_TO_REG_0( - .reg = REG_A6XX_VPC_SO_BUFFER_OFFSET(i), + .reg = VPC_SO_BUFFER_OFFSET(CHIP, i).reg, .shift_by_2 = CHIP == A6XX, .unk31 = true, )) @@ -424,7 +426,7 @@ fd6_emit_streamout(fd_cs &cs, struct fd6_emit *emit) assert_dt // After a draw HW would write the new offset to offset_bo fd_pkt4(cs, 2) - .add(A6XX_VPC_SO_FLUSH_BASE(i, offset_bo)); + .add(VPC_SO_FLUSH_BASE(CHIP, i, offset_bo)); so->reset &= ~(1 << i); @@ -465,6 +467,7 @@ fd6_emit_streamout(fd_cs &cs, struct fd6_emit *emit) assert_dt /** * Stuff that less frequently changes and isn't (yet) moved into stategroups */ +template static void fd6_emit_non_group(fd_cs &cs, struct fd6_emit *emit) assert_dt { @@ -485,18 +488,18 @@ fd6_emit_non_group(fd_cs &cs, struct fd6_emit *emit) assert_dt struct pipe_scissor_state *scissor = &ctx->viewport_scissor[i]; struct pipe_viewport_state *vp = & ctx->viewport[i]; - crb.add(A6XX_GRAS_CL_VIEWPORT_XOFFSET(i, vp->translate[0])); - crb.add(A6XX_GRAS_CL_VIEWPORT_XSCALE(i, vp->scale[0])); - crb.add(A6XX_GRAS_CL_VIEWPORT_YOFFSET(i, vp->translate[1])); - crb.add(A6XX_GRAS_CL_VIEWPORT_YSCALE(i, vp->scale[1])); - crb.add(A6XX_GRAS_CL_VIEWPORT_ZOFFSET(i, vp->translate[2])); - crb.add(A6XX_GRAS_CL_VIEWPORT_ZSCALE(i, vp->scale[2])); - crb.add(A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(i, .x = scissor->minx, .y = scissor->miny)); - crb.add(A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(i, .x = scissor->maxx, .y = scissor->maxy)); + crb.add(GRAS_CL_VIEWPORT_XOFFSET(CHIP, i, vp->translate[0])); + crb.add(GRAS_CL_VIEWPORT_XSCALE(CHIP, i, vp->scale[0])); + crb.add(GRAS_CL_VIEWPORT_YOFFSET(CHIP, i, vp->translate[1])); + crb.add(GRAS_CL_VIEWPORT_YSCALE(CHIP, i, vp->scale[1])); + crb.add(GRAS_CL_VIEWPORT_ZOFFSET(CHIP, i, vp->translate[2])); + crb.add(GRAS_CL_VIEWPORT_ZSCALE(CHIP, i, vp->scale[2])); + crb.add(GRAS_SC_VIEWPORT_SCISSOR_TL(CHIP, i, .x = scissor->minx, .y = scissor->miny)); + crb.add(GRAS_SC_VIEWPORT_SCISSOR_BR(CHIP, i, .x = scissor->maxx, .y = scissor->maxy)); } - crb.add(A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ(.horz = ctx->guardband.x, - .vert = ctx->guardband.y)); + crb.add(GRAS_CL_GUARDBAND_CLIP_ADJ(CHIP, .horz = ctx->guardband.x, + .vert = ctx->guardband.y)); } /* The clamp ranges are only used when the rasterizer wants depth @@ -511,18 +514,19 @@ fd6_emit_non_group(fd_cs &cs, struct fd6_emit *emit) assert_dt util_viewport_zmin_zmax(vp, ctx->rasterizer->clip_halfz, &zmin, &zmax); - crb.add(A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MIN(i, zmin)); - crb.add(A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MAX(i, zmax)); + crb.add(GRAS_CL_VIEWPORT_ZCLAMP_MIN(CHIP, i, zmin)); + crb.add(GRAS_CL_VIEWPORT_ZCLAMP_MAX(CHIP, i, zmax)); /* TODO: what to do about this and multi viewport ? */ if (i == 0) { - crb.add(A6XX_RB_VIEWPORT_ZCLAMP_MIN(zmin)); - crb.add(A6XX_RB_VIEWPORT_ZCLAMP_MAX(zmax)); + crb.add(RB_VIEWPORT_ZCLAMP_MIN(CHIP, zmin)); + crb.add(RB_VIEWPORT_ZCLAMP_MAX(CHIP, zmax)); } } } } +template static struct fd_ringbuffer* build_prim_mode(struct fd6_emit *emit, struct fd_context *ctx, bool gmem) assert_dt @@ -540,7 +544,7 @@ build_prim_mode(struct fd6_emit *emit, struct fd_context *ctx, bool gmem) } return fd_crb(ctx->batch->submit, 1) - .add(A6XX_GRAS_SC_CNTL( + .add(GRAS_SC_CNTL(CHIP, .ccusinglecachelinesize = 2, .single_prim_mode = (enum a6xx_single_prim_mode)prim_mode) ) @@ -592,7 +596,7 @@ fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit) fd6_state_take_group(&emit->state, state, FD6_GROUP_LRZ); break; case FD6_GROUP_SCISSOR: - state = build_scissor(emit); + state = build_scissor(emit); fd6_state_take_group(&emit->state, state, FD6_GROUP_SCISSOR); break; case FD6_GROUP_PROG: @@ -605,7 +609,7 @@ fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit) /* emit remaining streaming program state, ie. what depends on * other emit state, so cannot be pre-baked. */ - fd6_state_take_group(&emit->state, fd6_program_interp_state(emit), + fd6_state_take_group(&emit->state, fd6_program_interp_state(emit), FD6_GROUP_PROG_INTERP); break; case FD6_GROUP_RASTERIZER: @@ -626,7 +630,7 @@ fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit) fd6_state_take_group(&emit->state, state, FD6_GROUP_BLEND_COLOR); break; case FD6_GROUP_SAMPLE_LOCATIONS: - state = build_sample_locations(emit); + state = build_sample_locations(emit); fd6_state_take_group(&emit->state, state, FD6_GROUP_SAMPLE_LOCATIONS); break; case FD6_GROUP_VS_BINDLESS: @@ -687,15 +691,15 @@ fd6_emit_3d_state(fd_cs &cs, struct fd6_emit *emit) fd6_emit_streamout(cs, emit); break; case FD6_GROUP_PRIM_MODE_SYSMEM: - state = build_prim_mode(emit, ctx, false); + state = build_prim_mode(emit, ctx, false); fd6_state_take_group(&emit->state, state, FD6_GROUP_PRIM_MODE_SYSMEM); break; case FD6_GROUP_PRIM_MODE_GMEM: - state = build_prim_mode(emit, ctx, true); + state = build_prim_mode(emit, ctx, true); fd6_state_take_group(&emit->state, state, FD6_GROUP_PRIM_MODE_GMEM); break; case FD6_GROUP_NON_GROUP: - fd6_emit_non_group(cs, emit); + fd6_emit_non_group(cs, emit); break; default: break; @@ -786,9 +790,9 @@ fd6_emit_ccu_cntl(fd_cs &cs, struct fd_screen *screen, bool gmem) if (screen->info->a7xx.has_gmem_vpc_attr_buf) { fd_crb(cs, 3) - .add(VPC_ATTR_BUF_GMEM_SIZE(CHIP, .size_gmem = cfg->vpc_attr_buf_size)) - .add(VPC_ATTR_BUF_GMEM_BASE(CHIP, .base_gmem = cfg->vpc_attr_buf_offset)) - .add(PC_ATTR_BUF_GMEM_SIZE(CHIP, .size_gmem = cfg->vpc_attr_buf_size)); + .add(VPC_ATTR_BUF_GMEM_SIZE(CHIP, cfg->vpc_attr_buf_size)) + .add(VPC_ATTR_BUF_GMEM_BASE(CHIP, cfg->vpc_attr_buf_offset)) + .add(PC_ATTR_BUF_GMEM_SIZE(CHIP, cfg->vpc_attr_buf_size)); } } else { fd_pkt7(cs, CP_WAIT_FOR_IDLE, 0); @@ -887,7 +891,7 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs) ncrb.add(VPC_UNKNOWN_9211(CHIP)); } - ncrb.add(A6XX_GRAS_UNKNOWN_80AF()); + ncrb.add(GRAS_SC_SCREEN_SCISSOR_CNTL(CHIP)); ncrb.add(A6XX_VPC_UNKNOWN_9602()); /* These regs are blocked (CP_PROTECT) on a6xx: */ @@ -918,7 +922,7 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs) fd_crb crb(cs, 80); - crb.add(A6XX_SP_GFX_USIZE()); + crb.add(SP_GFX_USIZE(CHIP)); crb.add(A6XX_SP_UNKNOWN_B182()); crb.add(A6XX_RB_UNKNOWN_8E01(.dword = screen->info->a6xx.magic.RB_UNKNOWN_8E01)); @@ -942,10 +946,10 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs) crb.add(VPC_RAST_STREAM_CNTL(CHIP)); } crb.add(A6XX_RB_UNKNOWN_8811(.dword = 0x00000010)); - crb.add(A6XX_PC_MODE_CNTL(.dword=screen->info->a6xx.magic.PC_MODE_CNTL)); - crb.add(A6XX_GRAS_LRZ_PS_INPUT_CNTL()); + crb.add(PC_MODE_CNTL(CHIP, .dword=screen->info->a6xx.magic.PC_MODE_CNTL)); + crb.add(GRAS_LRZ_PS_INPUT_CNTL(CHIP)); crb.add(A6XX_GRAS_LRZ_PS_SAMPLEFREQ_CNTL()); - crb.add(A6XX_GRAS_UNKNOWN_8110(.dword = 0x2)); + crb.add(GRAS_MODE_CNTL(CHIP, .dword = 0x2)); crb.add(A6XX_RB_UNKNOWN_8818()); @@ -959,20 +963,20 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs) } crb.add(A6XX_RB_UNKNOWN_88F0()); - crb.add(A6XX_VPC_REPLACE_MODE_CNTL()); - crb.add(A6XX_VPC_UNKNOWN_9300()); - crb.add(A6XX_VPC_SO_OVERRIDE(true)); + crb.add(VPC_REPLACE_MODE_CNTL(CHIP)); + crb.add(VPC_ROTATION_CNTL(CHIP)); + crb.add(VPC_SO_OVERRIDE(CHIP, true)); crb.add(VPC_RAST_STREAM_CNTL(CHIP)); if (CHIP == A7XX) crb.add(VPC_RAST_STREAM_CNTL_V2(CHIP)); - crb.add(A6XX_PC_STEREO_RENDERING_CNTL()); + crb.add(PC_STEREO_RENDERING_CNTL(CHIP)); crb.add(A6XX_SP_UNKNOWN_B183()); - crb.add(A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL()); - crb.add(A6XX_GRAS_SU_VS_SIV_CNTL()); - crb.add(A6XX_GRAS_SC_CNTL(.ccusinglecachelinesize = 2)); + crb.add(GRAS_SU_CONSERVATIVE_RAS_CNTL(CHIP)); + crb.add(GRAS_SU_VS_SIV_CNTL(CHIP)); + crb.add(GRAS_SC_CNTL(CHIP, .ccusinglecachelinesize = 2)); if (CHIP == A6XX) { crb.add(VPC_UNKNOWN_9210(CHIP)); @@ -995,15 +999,15 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs) crb.add(A6XX_VFD_RENDER_MODE(RENDERING_PASS)); crb.add(A6XX_VFD_STEREO_RENDERING_CNTL()); - crb.add(A6XX_VPC_SO_CNTL()); + crb.add(VPC_SO_CNTL(CHIP)); - crb.add(A6XX_GRAS_LRZ_CNTL()); + crb.add(GRAS_LRZ_CNTL(CHIP)); if (CHIP >= A7XX) crb.add(GRAS_LRZ_CNTL2(CHIP)); crb.add(A6XX_RB_LRZ_CNTL()); crb.add(A6XX_RB_DEPTH_PLANE_CNTL()); - crb.add(A6XX_GRAS_SU_DEPTH_PLANE_CNTL()); + crb.add(GRAS_SU_DEPTH_PLANE_CNTL(CHIP)); /* Initialize VFD_VERTEX_BUFFER[n].SIZE to zero to avoid iova faults trying * to fetch from a VFD_VERTEX_BUFFER[n].BASE which we've potentially inherited @@ -1017,7 +1021,7 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs) crb.add(A6XX_TPL1_GFX_BORDER_COLOR_BASE(.bo = bcolor_mem)); crb.add(A6XX_TPL1_CS_BORDER_COLOR_BASE(.bo = bcolor_mem)); - crb.add(A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL()); + crb.add(PC_DGEN_SU_CONSERVATIVE_RAS_CNTL(CHIP)); if (CHIP >= A7XX) { /* Blob sets these two per draw. */ diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc index d064849969c..caf1ec27ff3 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc @@ -122,11 +122,11 @@ emit_mrt(fd_crb &crb, struct pipe_framebuffer_state *pfb, if (pfb->zsbuf.texture) max_layer_index = pfb->zsbuf.last_layer - pfb->zsbuf.first_layer; - crb.add(A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0(.color_format = mrt0_format)); + crb.add(GRAS_LRZ_MRT_BUFFER_INFO_0(CHIP, .color_format = mrt0_format)); crb.add(A6XX_RB_SRGB_CNTL(.dword = srgb_cntl)); crb.add(A6XX_SP_SRGB_CNTL(.dword = srgb_cntl)); - crb.add(A6XX_GRAS_CL_ARRAY_SIZE(max_layer_index)); + crb.add(GRAS_CL_ARRAY_SIZE(CHIP, max_layer_index)); } template @@ -161,7 +161,7 @@ emit_zs(fd_crb &crb, struct pipe_surface *zsbuf, const struct fd_gmem_stateobj * crb.add(A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH()); crb.add(A6XX_RB_DEPTH_BUFFER_BASE()); crb.add(A6XX_RB_DEPTH_GMEM_BASE(base)); - crb.add(A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt)); + crb.add(GRAS_SU_DEPTH_BUFFER_INFO(CHIP, .depth_format = fmt)); stencil = rsc; } else { @@ -176,7 +176,7 @@ emit_zs(fd_crb &crb, struct pipe_surface *zsbuf, const struct fd_gmem_stateobj * crb.add(A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(array_stride)); crb.add(A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset)); crb.add(A6XX_RB_DEPTH_GMEM_BASE(base)); - crb.add(A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt)); + crb.add(GRAS_SU_DEPTH_BUFFER_INFO(CHIP, .depth_format = fmt)); crb.add(A6XX_RB_DEPTH_FLAG_BUFFER_BASE( .bo = rsc->bo, @@ -216,7 +216,7 @@ emit_zs(fd_crb &crb, struct pipe_surface *zsbuf, const struct fd_gmem_stateobj * crb.add(A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH()); crb.add(A6XX_RB_DEPTH_BUFFER_BASE()); crb.add(A6XX_RB_DEPTH_GMEM_BASE()); - crb.add(A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE)); + crb.add(GRAS_SU_DEPTH_BUFFER_INFO(CHIP, .depth_format = DEPTH6_NONE)); crb.add(RB_STENCIL_BUFFER_INFO(CHIP, 0)); } } @@ -230,8 +230,8 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass) if (!subpass->lrz) { fd_crb crb(cs, 6); - crb.add(A6XX_GRAS_LRZ_BUFFER_BASE()); - crb.add(A6XX_GRAS_LRZ_BUFFER_PITCH()); + crb.add(GRAS_LRZ_BUFFER_BASE(CHIP)); + crb.add(GRAS_LRZ_BUFFER_PITCH(CHIP)); crb.add(A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE()); if (CHIP >= A7XX) crb.add(GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP)); @@ -252,8 +252,8 @@ emit_lrz(fd_cs &cs, struct fd_batch *batch, struct fd_batch_subpass *subpass) crb.attach_bo(subpass->lrz); - crb.add(A6XX_GRAS_LRZ_BUFFER_BASE(.bo = subpass->lrz)); - crb.add(A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = zsbuf->lrz_layout.lrz_pitch)); + crb.add(GRAS_LRZ_BUFFER_BASE(CHIP, .bo = subpass->lrz)); + crb.add(GRAS_LRZ_BUFFER_PITCH(CHIP, .pitch = zsbuf->lrz_layout.lrz_pitch)); crb.add(A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE( .bo = zsbuf->lrz_layout.lrz_fc_size ? subpass->lrz : NULL, .bo_offset = zsbuf->lrz_layout.lrz_fc_offset @@ -855,16 +855,17 @@ emit_conditional_ib(fd_cs &cs, struct fd_batch *batch, const struct fd_tile *til emit_marker6(cs, 6); } +template static void set_scissor(fd_cs &cs, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2) { fd_pkt4(cs, 2) - .add(A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1)) - .add(A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2)); + .add(GRAS_SC_WINDOW_SCISSOR_TL(CHIP, .x = x1, .y = y1)) + .add(GRAS_SC_WINDOW_SCISSOR_BR(CHIP, .x = x2, .y = y2)); fd_pkt4(cs, 2) - .add(A6XX_GRAS_A2D_SCISSOR_TL(.x = x1, .y = y1)) - .add(A6XX_GRAS_A2D_SCISSOR_BR(.x = x2, .y = y2)); + .add(GRAS_A2D_SCISSOR_TL(CHIP, .x = x1, .y = y1)) + .add(GRAS_A2D_SCISSOR_BR(CHIP, .x = x2, .y = y2)); } template @@ -905,7 +906,7 @@ set_bin_size(fd_crb &crb, const struct fd_gmem_stateobj *gmem, struct bin_size_p unsigned h = gmem ? gmem->bin_h : 0; if (CHIP == A6XX) { - crb.add(A6XX_GRAS_SC_BIN_CNTL( + crb.add(GRAS_SC_BIN_CNTL(CHIP, .binw = w, .binh = h, .render_mode = p.render_mode, .force_lrz_write_dis = p.force_lrz_write_dis, @@ -913,7 +914,7 @@ set_bin_size(fd_crb &crb, const struct fd_gmem_stateobj *gmem, struct bin_size_p .lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, )); } else { - crb.add(A6XX_GRAS_SC_BIN_CNTL( + crb.add(GRAS_SC_BIN_CNTL(CHIP, .binw = w, .binh = h, .render_mode = p.render_mode, .force_lrz_write_dis = p.force_lrz_write_dis, @@ -929,7 +930,7 @@ set_bin_size(fd_crb &crb, const struct fd_gmem_stateobj *gmem, struct bin_size_p .lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, )); /* no flag for RB_RESOLVE_CNTL_3... */ - crb.add(A6XX_RB_RESOLVE_CNTL_3(.binw = w, .binh = h)); + crb.add(RB_RESOLVE_CNTL_3(CHIP, .binw = w, .binh = h)); } template @@ -941,7 +942,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt assert(!batch->tessellation); - set_scissor(cs, 0, 0, gmem->width - 1, gmem->height - 1); + set_scissor(cs, 0, 0, gmem->width - 1, gmem->height - 1); emit_marker6(cs, 7); fd_pkt7(cs, CP_SET_MARKER, 1) @@ -1017,6 +1018,7 @@ emit_binning_pass(fd_cs &cs, struct fd_batch *batch) assert_dt } /* nregs: 7 */ +template static void emit_msaa(fd_crb &crb, unsigned nr) { @@ -1028,8 +1030,8 @@ emit_msaa(fd_crb &crb, unsigned nr) .msaa_disable = (samples == MSAA_ONE), )); - crb.add(A6XX_GRAS_SC_RAS_MSAA_CNTL(.samples = samples)); - crb.add(A6XX_GRAS_SC_DEST_MSAA_CNTL( + crb.add(GRAS_SC_RAS_MSAA_CNTL(CHIP, .samples = samples)); + crb.add(GRAS_SC_DEST_MSAA_CNTL(CHIP, .samples = samples, .msaa_disable = (samples == MSAA_ONE), )); @@ -1057,7 +1059,7 @@ fd7_emit_static_binning_regs(fd_cs &cs) ncrb.add(RB_UNKNOWN_8812(CHIP, 0x0)); ncrb.add(RB_CCU_DBG_ECO_CNTL(CHIP, 0x0)); ncrb.add(GRAS_UNKNOWN_8007(CHIP, 0x0)); - ncrb.add(A6XX_GRAS_UNKNOWN_8110(0x2)); + ncrb.add(GRAS_MODE_CNTL(CHIP, 0x2)); ncrb.add(RB_UNKNOWN_8E09(CHIP, 0x4)); ncrb.add(RB_CLEAR_TARGET(CHIP, .clear_mode = CLEAR_MODE_GMEM)); } @@ -1138,7 +1140,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt with_crb (cs, 150) { emit_zs(crb, &pfb->zsbuf, batch->gmem_state); emit_mrt(crb, pfb, batch->gmem_state); - emit_msaa(crb, pfb->samples); + emit_msaa(crb, pfb->samples); } patch_fb_read_gmem(batch); @@ -1150,7 +1152,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt if (use_hw_binning(batch)) { /* enable stream-out during binning pass: */ with_crb (cs, 4) { - crb.add(A6XX_VPC_SO_OVERRIDE(false)); + crb.add(VPC_SO_OVERRIDE(CHIP, false)); set_bin_size(crb, gmem, { .render_mode = BINNING_PASS, @@ -1164,7 +1166,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt with_crb (cs, 5) { /* and disable stream-out for draw pass: */ - crb.add(A6XX_VPC_SO_OVERRIDE(true)); + crb.add(VPC_SO_OVERRIDE(CHIP, true)); /* * NOTE: even if we detect VSC overflow and disable use of @@ -1208,7 +1210,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt } else { with_crb (cs, 4) { /* no binning pass, so enable stream-out for draw pass: */ - crb.add(A6XX_VPC_SO_OVERRIDE(false)); + crb.add(VPC_SO_OVERRIDE(CHIP, false)); set_bin_size(crb, gmem, { .render_mode = RENDERING_PASS, @@ -1261,7 +1263,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile) uint32_t x2 = tile->xoff + tile->bin_w - 1; uint32_t y2 = tile->yoff + tile->bin_h - 1; - set_scissor(cs, x1, y1, x2, y2); + set_scissor(cs, x1, y1, x2, y2); set_tessfactor_bo(cs, batch); fd6_emit_ccu_cntl(cs, screen, true); @@ -1269,7 +1271,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile) with_crb (cs, 150) { emit_zs(crb, &pfb->zsbuf, batch->gmem_state); emit_mrt(crb, pfb, batch->gmem_state); - emit_msaa(crb, pfb->samples); + emit_msaa(crb, pfb->samples); } if (use_hw_binning(batch)) { @@ -1304,7 +1306,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile) .add(0x0); with_crb (cs, 5) { - crb.add(A6XX_VPC_SO_OVERRIDE(true)); + crb.add(VPC_SO_OVERRIDE(CHIP, true)); /* * NOTE: even if we detect VSC overflow and disable use of @@ -1339,7 +1341,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile) /* no binning pass, so enable stream-out for draw pass:: */ fd_pkt4(cs, 1) - .add(A6XX_VPC_SO_OVERRIDE(false)); + .add(VPC_SO_OVERRIDE(CHIP, false)); } with_crb (cs, 7) { @@ -1932,7 +1934,7 @@ fd6_emit_tile_fini(struct fd_batch *batch) emit_common_fini(cs, batch); fd_pkt4(cs, 1) - .add(A6XX_GRAS_LRZ_CNTL(.enable = true)); + .add(GRAS_LRZ_CNTL(CHIP, .enable = true)); fd6_event_write(batch->ctx, cs, FD_LRZ_FLUSH); fd6_event_write(batch->ctx, cs, FD_CCU_CLEAN_BLIT_CACHE); @@ -2033,16 +2035,16 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt struct pipe_framebuffer_state *pfb = &batch->framebuffer; if (pfb->width > 0 && pfb->height > 0) - set_scissor(cs, 0, 0, pfb->width - 1, pfb->height - 1); + set_scissor(cs, 0, 0, pfb->width - 1, pfb->height - 1); else - set_scissor(cs, 0, 0, 0, 0); + set_scissor(cs, 0, 0, 0, 0); set_tessfactor_bo(cs, batch); if (CHIP >= A7XX) { /* Non-context regs: */ fd_pkt4(cs, 1) - .add(A6XX_GRAS_UNKNOWN_8110(0x2)); + .add(GRAS_MODE_CNTL(CHIP, 0x2)); } with_crb (cs, 12) { @@ -2061,7 +2063,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt } /* enable stream-out, with sysmem there is only one pass: */ - crb.add(A6XX_VPC_SO_OVERRIDE(false)); + crb.add(VPC_SO_OVERRIDE(CHIP, false)); } emit_marker6(cs, 7); @@ -2082,7 +2084,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt with_crb (cs, 150) { emit_zs(crb, &pfb->zsbuf, NULL); emit_mrt(crb, pfb, NULL); - emit_msaa(crb, pfb->samples); + emit_msaa(crb, pfb->samples); } emit_common_init(cs, batch); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc index 20c7b3a743c..b31ec4c36c4 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.cc @@ -255,6 +255,7 @@ FD_GENX(fd6_emit_shader); * Build a pre-baked state-obj to disable SO, so that we aren't dynamically * building this at draw time whenever we transition from SO enabled->disabled */ +template static void setup_stream_out_disable(struct fd_context *ctx) { @@ -265,16 +266,17 @@ setup_stream_out_disable(struct fd_context *ctx) fd_crb crb(ctx->pipe, nreg); - crb.add(A6XX_VPC_SO_MAPPING_WPTR()); - crb.add(A6XX_VPC_SO_CNTL()); + crb.add(VPC_SO_MAPPING_WPTR(CHIP)); + crb.add(VPC_SO_CNTL(CHIP)); if (ctx->screen->info->a6xx.tess_use_shared) { - crb.add(A6XX_PC_DGEN_SO_CNTL()); + crb.add(PC_DGEN_SO_CNTL(CHIP)); } fd6_context(ctx)->streamout_disable_stateobj = crb.ring(); } +template static void setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state, const struct ir3_shader_variant *v, @@ -341,7 +343,7 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state, fd_crb crb(ctx->pipe, nreg); - crb.add(A6XX_VPC_SO_CNTL( + crb.add(VPC_SO_CNTL(CHIP, .buf0_stream = 1 + strmout->output[0].stream, .buf1_stream = 1 + strmout->output[1].stream, .buf2_stream = 1 + strmout->output[2].stream, @@ -350,14 +352,14 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state, )); for (unsigned i = 0; i < 4; i++) - crb.add(A6XX_VPC_SO_BUFFER_STRIDE(i, strmout->stride[i])); + crb.add(VPC_SO_BUFFER_STRIDE(CHIP, i, strmout->stride[i])); bool first = true; BITSET_FOREACH_RANGE (start, end, valid_dwords, A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) { - crb.add(A6XX_VPC_SO_MAPPING_WPTR(.addr = start, .reset = first)); + crb.add(VPC_SO_MAPPING_WPTR(CHIP, .addr = start, .reset = first)); for (unsigned i = start; i < end; i++) { - crb.add(A6XX_VPC_SO_MAPPING_PORT(.dword = prog[i])); + crb.add(VPC_SO_MAPPING_PORT(CHIP, .dword = prog[i])); } first = false; } @@ -366,7 +368,7 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state, /* Possibly not tess_use_shared related, but the combination of * tess + xfb fails some tests if we don't emit this. */ - crb.add(A6XX_PC_DGEN_SO_CNTL(.stream_enable = true)); + crb.add(PC_DGEN_SO_CNTL(CHIP, .stream_enable = true)); } state->streamout_stateobj = crb.ring(); @@ -430,7 +432,7 @@ setup_config_stateobj(struct fd_context *ctx, struct fd6_program_state *state) crb.add(A6XX_SP_GS_CONFIG(.dword = sp_xs_config(state->gs))); crb.add(A6XX_SP_PS_CONFIG(.dword = sp_xs_config(state->fs))); - crb.add(A6XX_SP_GFX_USIZE(ir3_shader_num_uavs(state->fs))); + crb.add(SP_GFX_USIZE(CHIP, ir3_shader_num_uavs(state->fs))); state->config_stateobj = crb.ring(); } @@ -656,7 +658,7 @@ emit_vpc(fd_crb &crb, const struct program_builder *b) emit_vs_system_values(crb, b); for (unsigned i = 0; i < 4; i++) - crb.add(A6XX_VPC_VARYING_LM_TRANSFER_CNTL_DISABLE(i, ~linkage.varmask[i])); + crb.add(VPC_VARYING_LM_TRANSFER_CNTL_DISABLE(CHIP, i, ~linkage.varmask[i])); /* a6xx finds position/pointsize at the end */ const uint32_t position_regid = @@ -722,10 +724,10 @@ emit_vpc(fd_crb &crb, const struct program_builder *b) * program: */ if (do_streamout && !b->binning_pass) { - setup_stream_out(b->ctx, b->state, b->last_shader, &linkage); + setup_stream_out(b->ctx, b->state, b->last_shader, &linkage); if (!fd6_context(b->ctx)->streamout_disable_stateobj) - setup_stream_out_disable(b->ctx); + setup_stream_out_disable(b->ctx); } /* There is a hardware bug on a750 where STRIDE_IN_VPC of 5 to 8 in GS with @@ -838,14 +840,14 @@ emit_vpc(fd_crb &crb, const struct program_builder *b) CONDREG(view_regid, A6XX_GRAS_SU_VS_SIV_CNTL_WRITES_VIEW) }); - crb.add(A6XX_PC_PS_CNTL(b->fs->reads_primid)); + crb.add(PC_PS_CNTL(CHIP, b->fs->reads_primid)); if (CHIP >= A7XX) { - crb.add(A6XX_GRAS_UNKNOWN_8110(0x2)); + crb.add(GRAS_MODE_CNTL(CHIP, 0x2)); crb.add(SP_RENDER_CNTL(CHIP, .fs_disable = false)); } - crb.add(A6XX_VPC_PS_CNTL( + crb.add(VPC_PS_CNTL(CHIP, .numnonposvar = b->fs->total_in, .primidloc = linkage.primid_loc, .varying = !!b->fs->total_in, @@ -853,7 +855,7 @@ emit_vpc(fd_crb &crb, const struct program_builder *b) )); if (b->hs) { - crb.add(A6XX_PC_HS_PARAM_0(b->hs->tess.tcs_vertices_out)); + crb.add(PC_HS_PARAM_0(CHIP, b->hs->tess.tcs_vertices_out)); } if (b->gs) { @@ -869,7 +871,7 @@ emit_vpc(fd_crb &crb, const struct program_builder *b) vec4_size = b->gs->gs.vertices_in * DIV_ROUND_UP(prev_stage_output_size, 4); - crb.add(A6XX_PC_GS_PARAM_0( + crb.add(PC_GS_PARAM_0(CHIP, .gs_vertices_out = vertices_out, .gs_invocations = invocations, .gs_output = output, @@ -1039,7 +1041,7 @@ emit_fs_inputs(fd_crb &crb, const struct program_builder *b) need_size = true; } - crb.add(A6XX_GRAS_CL_INTERP_CNTL( + crb.add(GRAS_CL_INTERP_CNTL(CHIP, .ij_persp_pixel = VALIDREG(ij_regid[IJ_PERSP_PIXEL]), .ij_persp_centroid = VALIDREG(ij_regid[IJ_PERSP_CENTROID]), .ij_persp_sample = VALIDREG(ij_regid[IJ_PERSP_SAMPLE]), @@ -1067,7 +1069,7 @@ emit_fs_inputs(fd_crb &crb, const struct program_builder *b) .centerrhw = VALIDREG(ij_regid[IJ_PERSP_CENTER_RHW]) )); crb.add(A6XX_RB_PS_SAMPLEFREQ_CNTL(sample_shading)); - crb.add(A6XX_GRAS_LRZ_PS_INPUT_CNTL( + crb.add(GRAS_LRZ_PS_INPUT_CNTL(CHIP, .sampleid = VALIDREG(samp_id_regid), .fragcoordsamplemode = sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER, )); @@ -1160,7 +1162,7 @@ setup_stateobj(fd_cs &cs, const struct program_builder *b) fd_crb crb(cs, 100); - crb.add(A6XX_PC_STEREO_RENDERING_CNTL()); + crb.add(PC_STEREO_RENDERING_CNTL(CHIP)); emit_vfd_dest(crb, b->vs); emit_vpc(crb, b); @@ -1175,7 +1177,7 @@ setup_stateobj(fd_cs &cs, const struct program_builder *b) patch_control_points * b->vs->output_size / 4; /* Total attribute slots in HS incoming patch. */ - crb.add(A6XX_PC_HS_PARAM_1(patch_local_mem_size_16b)); + crb.add(PC_HS_PARAM_1(CHIP, patch_local_mem_size_16b)); const uint32_t wavesize = 64; const uint32_t vs_hs_local_mem_size = 16384; @@ -1214,23 +1216,25 @@ setup_stateobj(fd_cs &cs, const struct program_builder *b) else output = TESS_CW_TRIS; - crb.add(A6XX_PC_DS_PARAM( + crb.add(PC_DS_PARAM(CHIP, .spacing = fd6_gl2spacing(b->ds->tess.spacing), .output = output, )); } } +template static void emit_interp_state(fd_crb &crb, const struct fd6_program_state *state, bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable); +template static struct fd_ringbuffer * create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state) { fd_crb crb(ctx->pipe, 16); - emit_interp_state(crb, state, false, false, 0); + emit_interp_state(crb, state, false, false, 0); return crb.ring(); } @@ -1239,6 +1243,7 @@ create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state) * baked stateobj because of dependency on other gl state (rasterflat * or sprite-coord-replacement) */ +template struct fd_ringbuffer * fd6_program_interp_state(struct fd6_emit *emit) { @@ -1250,13 +1255,15 @@ fd6_program_interp_state(struct fd6_emit *emit) } else { fd_crb crb(emit->ctx->batch->submit, 16); - emit_interp_state(crb, state, emit->rasterflat, - emit->sprite_coord_mode, emit->sprite_coord_enable); + emit_interp_state(crb, state, emit->rasterflat, + emit->sprite_coord_mode, emit->sprite_coord_enable); return crb.ring(); } } +FD_GENX(fd6_program_interp_state); +template static void emit_interp_state(fd_crb &crb, const struct fd6_program_state *state, bool rasterflat, bool sprite_coord_mode, @@ -1332,10 +1339,10 @@ emit_interp_state(fd_crb &crb, const struct fd6_program_state *state, } for (int i = 0; i < 8; i++) - crb.add(A6XX_VPC_VARYING_INTERP_MODE_MODE(i, vinterp[i])); + crb.add(VPC_VARYING_INTERP_MODE_MODE(CHIP, i, vinterp[i])); for (int i = 0; i < 8; i++) - crb.add(A6XX_VPC_VARYING_REPLACE_MODE_MODE(i, vpsrepl[i])); + crb.add(VPC_VARYING_REPLACE_MODE_MODE(CHIP, i, vpsrepl[i])); } template @@ -1436,7 +1443,7 @@ fd6_program_create(void *data, const struct ir3_shader_variant *bs, fd_cs cs(state->stateobj); setup_stateobj(cs, &b); - state->interp_stateobj = create_interp_stateobj(ctx, state); + state->interp_stateobj = create_interp_stateobj(ctx, state); const struct ir3_stream_output_info *stream_output = &last_shader->stream_output; if (stream_output->num_outputs > 0) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.h b/src/gallium/drivers/freedreno/a6xx/fd6_program.h index 820d1cd68ab..cfdfcfcce94 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.h +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.h @@ -92,6 +92,7 @@ template void fd6_emit_shader(struct fd_context *ctx, fd_cs &cs, const struct ir3_shader_variant *so) assert_dt; +template struct fd_ringbuffer *fd6_program_interp_state(struct fd6_emit *emit) assert_dt; template diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_query.cc b/src/gallium/drivers/freedreno/a6xx/fd6_query.cc index ed07429db4c..a5b9a42bbb3 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_query.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_query.cc @@ -642,7 +642,7 @@ primitives_emitted_resume(struct fd_acc_query *aq, ASSERT_ALIGNED(struct fd6_primitives_sample, start[0], 32); fd_pkt4(cs, 2) - .add(A6XX_VPC_SO_QUERY_BASE(primitives_sample(aq, start[0]))); + .add(VPC_SO_QUERY_BASE(CHIP, primitives_sample(aq, start[0]))); fd6_event_write(batch->ctx, cs, FD_WRITE_PRIMITIVE_COUNTS); } @@ -683,7 +683,7 @@ primitives_emitted_pause(struct fd_acc_query *aq, ASSERT_ALIGNED(struct fd6_primitives_sample, stop[0], 32); fd_pkt4(cs, 2) - .add(A6XX_VPC_SO_QUERY_BASE(primitives_sample(aq, stop[0]))); + .add(VPC_SO_QUERY_BASE(CHIP, primitives_sample(aq, stop[0]))); fd6_event_write(batch->ctx, cs, FD_WRITE_PRIMITIVE_COUNTS); fd6_event_write(batch->ctx, cs, FD_CACHE_CLEAN); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.cc b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.cc index dc4aca442bb..fac474d0466 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.cc @@ -39,7 +39,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, unsigned nreg = (CHIP >= A7XX) ? 46 : 15; fd_crb crb(ctx->pipe, nreg); - crb.add(A6XX_GRAS_CL_CNTL( + crb.add(GRAS_CL_CNTL(CHIP, .znear_clip_disable = !cso->depth_clip_near, .zfar_clip_disable = !cso->depth_clip_far, .z_clamp_enable = cso->depth_clamp || CHIP >= A7XX, @@ -48,7 +48,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, ) ); - crb.add(A6XX_GRAS_SU_CNTL( + crb.add(GRAS_SU_CNTL(CHIP, .cull_front = cso->cull_face & PIPE_FACE_FRONT, .cull_back = cso->cull_face & PIPE_FACE_BACK, .front_cw = !cso->front_ccw, @@ -58,13 +58,13 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, ) ); - crb.add(A6XX_GRAS_SU_POINT_MINMAX(.min = psize_min, .max = psize_max, )); - crb.add(A6XX_GRAS_SU_POINT_SIZE(cso->point_size)); - crb.add(A6XX_GRAS_SU_POLY_OFFSET_SCALE(cso->offset_scale)); - crb.add(A6XX_GRAS_SU_POLY_OFFSET_OFFSET(cso->offset_units)); - crb.add(A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(cso->offset_clamp)); + crb.add(GRAS_SU_POINT_MINMAX(CHIP, .min = psize_min, .max = psize_max, )); + crb.add(GRAS_SU_POINT_SIZE(CHIP, cso->point_size)); + crb.add(GRAS_SU_POLY_OFFSET_SCALE(CHIP, cso->offset_scale)); + crb.add(GRAS_SU_POLY_OFFSET_OFFSET(CHIP, cso->offset_units)); + crb.add(GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(CHIP, cso->offset_clamp)); - crb.add(A6XX_PC_CNTL( + crb.add(PC_CNTL(CHIP, .primitive_restart = primitive_restart, .provoking_vtx_last = !cso->flatshade_first, ) @@ -91,7 +91,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, break; } - crb.add(A6XX_VPC_RAST_CNTL(mode)); + crb.add(VPC_RAST_CNTL(CHIP, mode)); crb.add(PC_DGEN_RAST_CNTL(CHIP, mode)); if (CHIP == A7XX || @@ -111,12 +111,12 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx, const unsigned num_viewports = 16; for (unsigned i = 0; i < num_viewports; i++) { - crb.add(A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MIN(i, 0.0f)); - crb.add(A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MAX(i, 1.0f)); + crb.add(GRAS_CL_VIEWPORT_ZCLAMP_MIN(CHIP, i, 0.0f)); + crb.add(GRAS_CL_VIEWPORT_ZCLAMP_MAX(CHIP, i, 1.0f)); } - crb.add(A6XX_RB_VIEWPORT_ZCLAMP_MIN(0.0f)); - crb.add(A6XX_RB_VIEWPORT_ZCLAMP_MAX(1.0f)); + crb.add(RB_VIEWPORT_ZCLAMP_MIN(CHIP, 0.0f)); + crb.add(RB_VIEWPORT_ZCLAMP_MAX(CHIP, 1.0f)); } if (CHIP == A6XX && ctx->screen->info->a6xx.has_legacy_pipeline_shading_rate) { diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.cc b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.cc index 85967e0ae27..f2b077dc267 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_zsa.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_zsa.cc @@ -209,7 +209,7 @@ fd6_zsa_state_create(struct pipe_context *pctx, .zfail_bf = fd_stencil_op(bs->zfail_op), )); - crb.add(A6XX_GRAS_SU_STENCIL_CNTL(cso->stencil[0].enabled)); + crb.add(GRAS_SU_STENCIL_CNTL(CHIP, cso->stencil[0].enabled)); crb.add(A6XX_RB_STENCIL_MASK(.mask = fs->valuemask, .bfmask = bs->valuemask)); crb.add(A6XX_RB_STENCIL_WRITE_MASK(.wrmask = fs->writemask, .bfwrmask = bs->writemask)); @@ -222,7 +222,7 @@ fd6_zsa_state_create(struct pipe_context *pctx, .z_bounds_enable = cso->depth_bounds_test, )); - crb.add(A6XX_GRAS_SU_DEPTH_CNTL(cso->depth_enabled)); + crb.add(GRAS_SU_DEPTH_CNTL(CHIP, cso->depth_enabled)); if (CHIP >= A7XX && !depth_clamp_enable) { crb.add(A6XX_RB_DEPTH_BOUND_MIN(0.0f));