From acdd6a2a6c3882ef6fa3acf612f9d55eaf55583e Mon Sep 17 00:00:00 2001 From: Patrick Lerda Date: Tue, 25 Apr 2023 16:47:23 +0200 Subject: [PATCH] radeonsi: set proper drm_amdgpu_cs_chunk_fence alignment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 'struct drm_amdgpu_cs_chunk_fence' is processed as 'struct drm_amdgpu_cs_chunk_data' which is a union. This change ensures the proper alignment for this structure to be processed as 'struct drm_amdgpu_cs_chunk_data'. The presence of __u64 as one member of 'struct drm_amdgpu_cs_chunk_data' makes the whole structure expected to be 64-bit aligned. This is a minor issue detected by the gcc sanitizer (ubsan), for instance at the libdrm library: ../amdgpu/amdgpu_cs.c:937:26: runtime error: member access within misaligned address 0x63100001484c for type 'struct drm_amdgpu_cs_chunk_data', which requires 8 byte alignment 0x63100001484c: note: pointer points here 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ^ Fixes: ae7e4d7619e0 ("amd: rename ring_type --> amd_ip_type and match the kernel enum values") Signed-off-by: Patrick Lerda Reviewed-by: Marek Olšák Part-of: --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h index 5038463db40..bd698bf4fe7 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h @@ -131,8 +131,12 @@ struct amdgpu_cs { struct amdgpu_ib main; /* must be first because this is inherited */ struct amdgpu_winsys *ws; struct amdgpu_ctx *ctx; - enum amd_ip_type ip_type; + + /* + * Ensure a 64-bit alignment for drm_amdgpu_cs_chunk_fence. + */ struct drm_amdgpu_cs_chunk_fence fence_chunk; + enum amd_ip_type ip_type; /* We flip between these two CS. While one is being consumed * by the kernel in another thread, the other one is being filled