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radv: Merge VGT_GS_MODE computation with PM4 generation.

Browse source 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Bas Nieuwenhuizen 2018-01-15 14:27:12 +01:00
parent 4ae6a8b0cd
commit acbaef3005
2 changed files with 25 additions and 28 deletions
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51
src/amd/vulkan/radv_pipeline.c
View file

@ -1558,26 +1558,6 @@ static const struct ac_vs_output_info *get_vs_output_info(const struct radv_pipe
return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
}
static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline)
{
const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
pipeline->graphics.vgt_primitiveid_en = false;
pipeline->graphics.vgt_gs_mode = 0;
if (radv_pipeline_has_gs(pipeline)) {
struct radv_shader_variant *gs =
pipeline->shaders[MESA_SHADER_GEOMETRY];
pipeline->graphics.vgt_gs_mode =
ac_vgt_gs_mode(gs->info.gs.vertices_out,
pipeline->device->physical_device->rad_info.chip_class);
} else if (outinfo->export_prim_id) {
pipeline->graphics.vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
pipeline->graphics.vgt_primitiveid_en = true;
}
}
static void
radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
{
@ -2466,6 +2446,30 @@ radv_pipeline_generate_multisample_state(struct radeon_winsys_cs *cs,
}
}
static void
radv_pipeline_generate_vgt_gs_mode(struct radeon_winsys_cs *cs,
const struct radv_pipeline *pipeline)
{
const struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline);
uint32_t vgt_primitiveid_en = false;
uint32_t vgt_gs_mode = 0;
if (radv_pipeline_has_gs(pipeline)) {
const struct radv_shader_variant *gs =
pipeline->shaders[MESA_SHADER_GEOMETRY];
vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
pipeline->device->physical_device->rad_info.chip_class);
} else if (outinfo->export_prim_id) {
vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
vgt_primitiveid_en = true;
}
radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
}
static void
radv_pipeline_generate_hw_vs(struct radeon_winsys_cs *cs,
struct radv_pipeline *pipeline,
@ -2595,8 +2599,6 @@ radv_pipeline_generate_vertex_shader(struct radeon_winsys_cs *cs,
{
struct radv_shader_variant *vs;
radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
/* Skip shaders merged into HS/GS */
vs = pipeline->shaders[MESA_SHADER_VERTEX];
if (!vs)
@ -2685,8 +2687,6 @@ radv_pipeline_generate_geometry_shader(struct radeon_winsys_cs *cs,
struct radv_shader_variant *gs;
uint64_t va;
radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
if (!gs)
return;
@ -2957,6 +2957,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
radv_pipeline_generate_blend_state(&pipeline->cs, pipeline, blend);
radv_pipeline_generate_raster_state(&pipeline->cs, pipeline);
radv_pipeline_generate_multisample_state(&pipeline->cs, pipeline);
radv_pipeline_generate_vgt_gs_mode(&pipeline->cs, pipeline);
radv_pipeline_generate_vertex_shader(&pipeline->cs, pipeline, tess);
radv_pipeline_generate_tess_shaders(&pipeline->cs, pipeline, tess);
radv_pipeline_generate_geometry_shader(&pipeline->cs, pipeline);
@ -3191,8 +3192,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
}
calculate_vgt_gs_mode(pipeline);
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
if (pipeline->shaders[i]) {
pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;

2
src/amd/vulkan/radv_private.h
View file

@ -1204,8 +1204,6 @@ struct radv_pipeline {
uint32_t spi_baryc_cntl;
unsigned prim;
unsigned gs_out;
uint32_t vgt_gs_mode;
bool vgt_primitiveid_en;
bool prim_restart_enable;
unsigned esgs_ring_size;
unsigned gsvs_ring_size;