isl: Enable Tigerlake HDC:L1 caches via MOCS in various cases.

Thanks to Felix Degrood for discovering that we missed enabling this
additional caching on Tigerlake!  Felix also benchmarked the changes.

We now use MOCS 48 (HDC:L1 + L3 + LLC) for render targets, textures,
and pull constant buffers.  We leave storage buffers & images, as well
as stateless messages, using the previous MOCS 2 value.  We can't use
HDC:L1 with atomics, and we don't know a priori whether storage buffers
will be used with atomics or not.  Similarly, the Vulkan buffer device
address feature allows atomics to be performed on buffers via stateless
messages, and we only can control MOCS at the base address level, so
we can't do much there.

This is closer to what the Windows Vulkan and OpenGL drivers do,
though it isn't quite the same - they also disable LLC in some cases,
but we observed this to have noticable performance regressions when
we tried (though a couple titles benefited).  We may try experiment
with that in the future.

Improves performance in a number of titles:

- Unreal Engine 4 Shooter Demo   [VK]: 11.8%
- Witcher 3                    [DXVK]:  3.9%
- Rise of the Tomb Raider        [VK]:  1.5%
- Shadow of the Tomb Raider      [VK]:  1.0%
- Grand Theft Auto V           [DXVK]:  0.8%

We did not observe any performance regressions.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7104>

src/intel/isl/isl.c

@@ -112,6 +112,9 @@ isl_device_setup_mocs(struct isl_device *dev)
          dev->mocs.external = 3 << 1;
          /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
          dev->mocs.internal = 2 << 1;
+
+         /* L1 - HDC:L1 + L3 + LLC */
+         dev->mocs.l1_hdc_l3_llc = 48 << 1;
       }
    } else if (dev->info->gen >= 9) {
       /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
@@ -160,6 +163,24 @@ isl_device_setup_mocs(struct isl_device *dev)
 uint32_t
 isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage)
 {
+   if (dev->info->gen >= 12 && !dev->info->is_dg1) {
+      if (usage & ISL_SURF_USAGE_STAGING_BIT)
+         return dev->mocs.internal;
+
+      /* Using L1:HDC for storage buffers breaks Vulkan memory model
+       * tests that use shader atomics.  This isn't likely to work out,
+       * and we can't know a priori whether they'll be used.  So just
+       * continue with ordinary internal MOCS for now.
+       */
+      if (usage & ISL_SURF_USAGE_STORAGE_BIT)
+         return dev->mocs.internal;
+
+      if (usage & (ISL_SURF_USAGE_CONSTANT_BUFFER_BIT |
+                   ISL_SURF_USAGE_RENDER_TARGET_BIT |
+                   ISL_SURF_USAGE_TEXTURE_BIT))
+         return dev->mocs.l1_hdc_l3_llc;
+   }
+
    return dev->mocs.internal;
 }
 

src/intel/isl/isl.h

@@ -1076,6 +1076,7 @@ struct isl_device {
    struct {
       uint32_t internal;
       uint32_t external;
+      uint32_t l1_hdc_l3_llc;
    } mocs;
 };