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nir: fix nir_const_value_as_uint bit size in load/store vectorizer tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>
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2 changed files with 6 additions and 4 deletions
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@ -38,6 +38,8 @@
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* - It won't turn four consecutive vec3 loads into 3 vec4 loads.
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* - It doesn't do global vectorization.
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* Handling these cases probably wouldn't provide much benefit though.
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*
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* This probably doesn't handle big-endian GPUs correctly.
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*/
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#include "nir.h"
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@ -961,10 +961,10 @@ TEST_F(nir_load_store_vectorize_test, ssbo_store_adjacent_8_8_16)
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ASSERT_EQ(val->bit_size, 8);
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ASSERT_EQ(val->num_components, 4);
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nir_const_value *cv = nir_instr_as_load_const(val->parent_instr)->value;
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ASSERT_EQ(nir_const_value_as_uint(cv[0], 32), 0x10);
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ASSERT_EQ(nir_const_value_as_uint(cv[1], 32), 0x20);
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ASSERT_EQ(nir_const_value_as_uint(cv[2], 32), 0x30);
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ASSERT_EQ(nir_const_value_as_uint(cv[3], 32), 0x0);
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ASSERT_EQ(nir_const_value_as_uint(cv[0], 8), 0x10);
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ASSERT_EQ(nir_const_value_as_uint(cv[1], 8), 0x20);
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ASSERT_EQ(nir_const_value_as_uint(cv[2], 8), 0x30);
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ASSERT_EQ(nir_const_value_as_uint(cv[3], 8), 0x0);
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}
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TEST_F(nir_load_store_vectorize_test, ssbo_store_adjacent_32_32_64)
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