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anv: Use dirty bits for dynamic state tracking

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Previously, we assumed that the dirty bit was always 1 << VK_DYNAMIC_*
and this assumption is about to be false.  Extensions which define new
VK_DYNAMIC_* enums won't be nice and tightly packed which this really
requires.  Instead, add functions to don the conversions and rework the
bits a bit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
This commit is contained in:
Jason Ekstrand 2019-05-22 18:25:50 -05:00
parent aa13f75f01
commit abf9e10488
3 changed files with 64 additions and 23 deletions
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20
src/intel/vulkan/anv_cmd_buffer.c
View file

@ -77,39 +77,39 @@ const struct anv_dynamic_state default_dynamic_state = {
void
anv_dynamic_state_copy(struct anv_dynamic_state *dest,
const struct anv_dynamic_state *src,
uint32_t copy_mask)
anv_cmd_dirty_mask_t copy_mask)
{
if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT) {
dest->viewport.count = src->viewport.count;
typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
src->viewport.count);
}
if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_SCISSOR) {
dest->scissor.count = src->scissor.count;
typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
src->scissor.count);
}
if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
dest->line_width = src->line_width;
if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
dest->depth_bias = src->depth_bias;
if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
typed_memcpy(dest->blend_constants, src->blend_constants, 4);
if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
dest->depth_bounds = src->depth_bounds;
if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK)
dest->stencil_compare_mask = src->stencil_compare_mask;
if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)
dest->stencil_write_mask = src->stencil_write_mask;
if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)
dest->stencil_reference = src->stencil_reference;
}

24
src/intel/vulkan/anv_pipeline.c
View file

@ -1505,8 +1505,10 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline,
if (pCreateInfo->pDynamicState) {
/* Remove all of the states that are marked as dynamic */
uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
for (uint32_t s = 0; s < count; s++)
states &= ~(1 << pCreateInfo->pDynamicState->pDynamicStates[s]);
for (uint32_t s = 0; s < count; s++) {
states &= ~anv_cmd_dirty_bit_for_vk_dynamic_state(
pCreateInfo->pDynamicState->pDynamicStates[s]);
}
}
struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
@ -1520,26 +1522,26 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline,
assert(pCreateInfo->pViewportState);
dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
if (states & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT) {
typed_memcpy(dynamic->viewport.viewports,
pCreateInfo->pViewportState->pViewports,
pCreateInfo->pViewportState->viewportCount);
}
dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
if (states & ANV_CMD_DIRTY_DYNAMIC_SCISSOR) {
typed_memcpy(dynamic->scissor.scissors,
pCreateInfo->pViewportState->pScissors,
pCreateInfo->pViewportState->scissorCount);
}
}
if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
if (states & ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH) {
assert(pCreateInfo->pRasterizationState);
dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
}
if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS)) {
if (states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS) {
assert(pCreateInfo->pRasterizationState);
dynamic->depth_bias.bias =
pCreateInfo->pRasterizationState->depthBiasConstantFactor;
@ -1567,7 +1569,7 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline,
!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
assert(pCreateInfo->pColorBlendState);
if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
if (states & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
typed_memcpy(dynamic->blend_constants,
pCreateInfo->pColorBlendState->blendConstants, 4);
}
@ -1588,28 +1590,28 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline,
subpass->depth_stencil_attachment) {
assert(pCreateInfo->pDepthStencilState);
if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
if (states & ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS) {
dynamic->depth_bounds.min =
pCreateInfo->pDepthStencilState->minDepthBounds;
dynamic->depth_bounds.max =
pCreateInfo->pDepthStencilState->maxDepthBounds;
}
if (states & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK)) {
if (states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK) {
dynamic->stencil_compare_mask.front =
pCreateInfo->pDepthStencilState->front.compareMask;
dynamic->stencil_compare_mask.back =
pCreateInfo->pDepthStencilState->back.compareMask;
}
if (states & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) {
if (states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK) {
dynamic->stencil_write_mask.front =
pCreateInfo->pDepthStencilState->front.writeMask;
dynamic->stencil_write_mask.back =
pCreateInfo->pDepthStencilState->back.writeMask;
}
if (states & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE)) {
if (states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE) {
dynamic->stencil_reference.front =
pCreateInfo->pDepthStencilState->front.reference;
dynamic->stencil_reference.back =

43
src/intel/vulkan/anv_private.h
View file

@ -1947,7 +1947,6 @@ enum anv_cmd_dirty_bits {
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
ANV_CMD_DIRTY_DYNAMIC_ALL = (1 << 9) - 1,
ANV_CMD_DIRTY_PIPELINE = 1 << 9,
ANV_CMD_DIRTY_INDEX_BUFFER = 1 << 10,
ANV_CMD_DIRTY_RENDER_TARGETS = 1 << 11,
@ -1955,6 +1954,46 @@ enum anv_cmd_dirty_bits {
};
typedef uint32_t anv_cmd_dirty_mask_t;
#define ANV_CMD_DIRTY_DYNAMIC_ALL \
(ANV_CMD_DIRTY_DYNAMIC_VIEWPORT | \
ANV_CMD_DIRTY_DYNAMIC_SCISSOR | \
ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH | \
ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS | \
ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | \
ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | \
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK | \
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK | \
ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)
static inline enum anv_cmd_dirty_bits
anv_cmd_dirty_bit_for_vk_dynamic_state(VkDynamicState vk_state)
{
switch (vk_state) {
case VK_DYNAMIC_STATE_VIEWPORT:
return ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
case VK_DYNAMIC_STATE_SCISSOR:
return ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
case VK_DYNAMIC_STATE_LINE_WIDTH:
return ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
case VK_DYNAMIC_STATE_DEPTH_BIAS:
return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
return ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
return ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
return ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
return ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
return ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
default:
assert(!"Unsupported dynamic state");
return 0;
}
}
enum anv_pipe_bits {
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT = (1 << 0),
ANV_PIPE_STALL_AT_SCOREBOARD_BIT = (1 << 1),
@ -2737,7 +2776,7 @@ struct anv_pipeline {
struct anv_batch batch;
uint32_t batch_data[512];
struct anv_reloc_list batch_relocs;
uint32_t dynamic_state_mask;
anv_cmd_dirty_mask_t dynamic_state_mask;
struct anv_dynamic_state dynamic_state;
struct anv_subpass * subpass;