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ac: add radeon_info::is_amdgpu instead of checking drm_major == 3

Browse source 
and clean up

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Marek Olšák 2019-06-11 22:49:18 -04:00
parent bbbbea243a
commit abe9a51d27
19 changed files with 33 additions and 77 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/amd/common/ac_gpu_info.c
View file

@ -117,6 +117,9 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->pci_func = devinfo->businfo.pci->func;
drmFreeDevice(&devinfo);
assert(info->drm_major == 3);
info->is_amdgpu = true;
/* Query hardware and driver information. */
r = amdgpu_query_gpu_info(dev, amdinfo);
if (r) {
@ -161,7 +164,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
return false;
}
if (info->drm_major == 3 && info->drm_minor >= 17) {
if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
@ -169,7 +172,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
if (info->drm_major == 3 && info->drm_minor >= 17) {
if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
@ -177,7 +180,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
if (info->drm_major == 3 && info->drm_minor >= 17) {
if (info->drm_minor >= 17) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
@ -185,7 +188,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
}
}
if (info->drm_major == 3 && info->drm_minor >= 27) {
if (info->drm_minor >= 27) {
r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
@ -744,7 +747,7 @@ ac_get_raster_config(struct radeon_info *info,
/* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
* This decreases performance by up to 50% when the RB is the bottleneck.
*/
if (info->family == CHIP_KAVERI && info->drm_major == 2)
if (info->family == CHIP_KAVERI && !info->is_amdgpu)
raster_config = 0x00000000;
/* Fiji: Old kernels have incorrect tiling config. This decreases

1
src/amd/common/ac_gpu_info.h
View file

@ -99,6 +99,7 @@ struct radeon_info {
uint32_t drm_major; /* version */
uint32_t drm_minor;
uint32_t drm_patchlevel;
bool is_amdgpu;
bool has_userptr;
bool has_syncobj;
bool has_syncobj_wait_for_submit;

5
src/amd/vulkan/radv_debug.c
View file

@ -111,14 +111,11 @@ radv_dump_debug_registers(struct radv_device *device, FILE *f)
{
struct radeon_info *info = &device->physical_device->rad_info;
if (info->drm_major == 2 && info->drm_minor < 42)
return; /* no radeon support */
fprintf(f, "Memory-mapped registers:\n");
radv_dump_mmapped_reg(device, f, R_008010_GRBM_STATUS);
/* No other registers can be read on DRM < 3.1.0. */
if (info->drm_major < 3 || info->drm_minor < 1) {
if (info->drm_minor < 1) {
fprintf(f, "\n");
return;
}

6
src/gallium/drivers/r600/r600_buffer_common.c
View file

@ -126,8 +126,7 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
/* Older kernels didn't always flush the HDP cache before
* CS execution
*/
if (rscreen->info.drm_major == 2 &&
rscreen->info.drm_minor < 40) {
if (rscreen->info.drm_minor < 40) {
res->domains = RADEON_DOMAIN_GTT;
res->flags |= RADEON_FLAG_GTT_WC;
break;
@ -154,8 +153,7 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
* ensures all CPU writes finish before the GPU
* executes a command stream.
*/
if (rscreen->info.drm_major == 2 &&
rscreen->info.drm_minor < 40)
if (rscreen->info.drm_minor < 40)
res->domains = RADEON_DOMAIN_GTT;
}

2
src/gallium/drivers/r600/r600_pipe.c
View file

@ -322,7 +322,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
return 64 * 1024 * 1024;
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
return rscreen->b.info.drm_minor >= 43;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;

46
src/gallium/drivers/r600/r600_pipe_common.c
View file

@ -345,48 +345,12 @@ void r600_postflush_resume_features(struct r600_common_context *ctx)
r600_resume_queries(ctx);
}
static void r600_add_fence_dependency(struct r600_common_context *rctx,
struct pipe_fence_handle *fence)
{
struct radeon_winsys *ws = rctx->ws;
if (rctx->dma.cs)
ws->cs_add_fence_dependency(rctx->dma.cs, fence, 0);
ws->cs_add_fence_dependency(rctx->gfx.cs, fence, 0);
}
static void r600_fence_server_sync(struct pipe_context *ctx,
struct pipe_fence_handle *fence)
{
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
/* Only amdgpu needs to handle fence dependencies (for fence imports).
* radeon synchronizes all rings by default and will not implement
/* radeon synchronizes all rings by default and will not implement
* fence imports.
*/
if (rctx->screen->info.drm_major == 2)
return;
/* Only imported fences need to be handled by fence_server_sync,
* because the winsys handles synchronizations automatically for BOs
* within the process.
*
* Simply skip unflushed fences here, and the winsys will drop no-op
* dependencies (i.e. dependencies within the same ring).
*/
if (rfence->gfx_unflushed.ctx)
return;
/* All unflushed commands will not start execution before
* this fence dependency is signalled.
*
* Should we flush the context to allow more GPU parallelism?
*/
if (rfence->sdma)
r600_add_fence_dependency(rctx, rfence->sdma);
if (rfence->gfx)
r600_add_fence_dependency(rctx, rfence->gfx);
}
static void r600_flush_from_st(struct pipe_context *ctx,
@ -1227,12 +1191,8 @@ static void r600_query_memory_info(struct pipe_screen *screen,
info->device_memory_evicted =
ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
if (rscreen->info.drm_major == 3 && rscreen->info.drm_minor >= 4)
info->nr_device_memory_evictions =
ws->query_value(ws, RADEON_NUM_EVICTIONS);
else
/* Just return the number of evicted 64KB pages. */
info->nr_device_memory_evictions = info->device_memory_evicted / 64;
/* Just return the number of evicted 64KB pages. */
info->nr_device_memory_evictions = info->device_memory_evicted / 64;
}
struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,

2
src/gallium/drivers/r600/r600_query.c
View file

@ -2031,7 +2031,7 @@ static const struct pipe_driver_query_info r600_driver_query_list[] = {
static unsigned r600_get_num_queries(struct r600_common_screen *rscreen)
{
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42)
if (rscreen->info.drm_minor >= 42)
return ARRAY_SIZE(r600_driver_query_list);
else
return ARRAY_SIZE(r600_driver_query_list) - 25;

2
src/gallium/drivers/r600/r600_texture.c
View file

@ -762,7 +762,7 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
rtex->surface.htile_size = 0;
if (rscreen->chip_class <= EVERGREEN &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
rscreen->info.drm_minor < 26)
return;
/* HW bug on R6xx. */

3
src/gallium/drivers/r600/radeon_uvd.c
View file

@ -1314,8 +1314,7 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
if (!dec)
return NULL;
if (info.drm_major < 3)
dec->use_legacy = true;
dec->use_legacy = true;
dec->base = *templ;
dec->base.context = context;

5
src/gallium/drivers/r600/radeon_vce.c
View file

@ -411,10 +411,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
if (!enc)
return NULL;
if (rscreen->info.drm_major == 3)
enc->use_vm = true;
if ((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 42) ||
rscreen->info.drm_major == 3)
if (rscreen->info.drm_minor >= 42)
enc->use_vui = true;
enc->base = *templ;

2
src/gallium/drivers/radeon/radeon_uvd.c
View file

@ -1250,7 +1250,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
if (!dec)
return NULL;
if (sctx->screen->info.drm_major < 3)
if (!sctx->screen->info.is_amdgpu)
dec->use_legacy = true;
dec->base = *templ;

6
src/gallium/drivers/radeon/radeon_vce.c
View file

@ -410,10 +410,10 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
if (!enc)
return NULL;
if (sscreen->info.drm_major == 3)
if (sscreen->info.is_amdgpu)
enc->use_vm = true;
if ((sscreen->info.drm_major == 2 && sscreen->info.drm_minor >= 42) ||
sscreen->info.drm_major == 3)
if ((!sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 42) ||
sscreen->info.is_amdgpu)
enc->use_vui = true;
if (sscreen->info.family >= CHIP_TONGA &&
sscreen->info.family != CHIP_STONEY &&

2
src/gallium/drivers/radeonsi/si_buffer.c
View file

@ -155,7 +155,7 @@ void si_init_resource_fields(struct si_screen *sscreen,
* persistent buffers into GTT to prevent VRAM CPU page faults.
*/
if (!sscreen->info.kernel_flushes_hdp_before_ib ||
sscreen->info.drm_major == 2)
!sscreen->info.is_amdgpu)
res->domains = RADEON_DOMAIN_GTT;
}

2
src/gallium/drivers/radeonsi/si_debug.c
View file

@ -322,7 +322,7 @@ static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
/* No other registers can be read on DRM < 3.1.0. */
if (sctx->screen->info.drm_major < 3 ||
if (!sctx->screen->info.is_amdgpu ||
sctx->screen->info.drm_minor < 1) {
fprintf(f, "\n");
return;

4
src/gallium/drivers/radeonsi/si_get.c
View file

@ -628,7 +628,7 @@ static int si_get_video_param(struct pipe_screen *screen,
return true;
if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
return false;
if (!(sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 19)) {
if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
RVID_ERR("No MJPEG support for the kernel version\n");
return false;
}
@ -920,7 +920,7 @@ static void si_query_memory_info(struct pipe_screen *screen,
info->device_memory_evicted =
ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
if (sscreen->info.drm_major == 3 && sscreen->info.drm_minor >= 4)
if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
info->nr_device_memory_evictions =
ws->query_value(ws, RADEON_NUM_EVICTIONS);
else

4
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -673,7 +673,7 @@ static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
* implementation for fence_server_sync is incomplete. */
return threaded_context_create(ctx, &sscreen->pool_transfers,
si_replace_buffer_storage,
sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
sscreen->info.is_amdgpu ? si_create_fence : NULL,
&((struct si_context*)ctx)->tc);
}
@ -1060,7 +1060,7 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
* on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
* SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/
sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
sscreen->info.drm_major == 3;
sscreen->info.is_amdgpu;
sscreen->has_distributed_tess =
sscreen->info.chip_class >= GFX8 &&

2
src/gallium/drivers/radeonsi/si_query.c
View file

@ -1819,7 +1819,7 @@ static struct pipe_driver_query_info si_driver_query_list[] = {
static unsigned si_get_num_queries(struct si_screen *sscreen)
{
/* amdgpu */
if (sscreen->info.drm_major == 3) {
if (sscreen->info.is_amdgpu) {
if (sscreen->info.chip_class >= GFX8)
return ARRAY_SIZE(si_driver_query_list);
else

2
src/gallium/drivers/radeonsi/si_state.c
View file

@ -4991,7 +4991,7 @@ static void si_init_config(struct si_context *sctx)
/* GFX6, radeon kernel disabled CLEAR_STATE. */
assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
sscreen->info.drm_major != 3);
!sscreen->info.is_amdgpu);
if (!pm4)
return;

1
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View file

@ -166,6 +166,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.drm_major = version->version_major;
ws->info.drm_minor = version->version_minor;
ws->info.drm_patchlevel = version->version_patchlevel;
ws->info.is_amdgpu = false;
drmFreeVersion(version);
/* Get PCI ID. */