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i915g: s/hw_tiled/tiling

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More in line with other intel drivers.

Change to use enum by Jakob Bornecrantz.

Reviewed-by: Jakob Bornecrantz <wallbraker@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Jakob Bornecrantz <wallbraker@gmail.com>
This commit is contained in:
Daniel Vetter 2010-11-19 23:38:19 +01:00 • committed by Jakob Bornecrantz
parent f77a2690b4
commit aba728eb25
2 changed files with 7 additions and 6 deletions
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5
src/gallium/drivers/i915/i915_resource.h
View file

@ -32,6 +32,7 @@ struct i915_screen;
#include "util/u_transfer.h"
#include "util/u_debug.h"
#include "i915_winsys.h"
struct i915_context;
@ -52,12 +53,12 @@ struct i915_buffer {
struct i915_texture {
struct u_resource b;
/* tiling flags */
enum i915_winsys_buffer_tile tiling;
unsigned stride;
unsigned depth_stride; /* per-image on i945? */
unsigned total_nblocksy;
unsigned hw_tiled; /**< tiled with hardware fences */
unsigned nr_images[I915_MAX_TEXTURE_2D_LEVELS];
/* Explicitly store the offset of each image for each cube face or

8
src/gallium/drivers/i915/i915_resource_texture.c
View file

@ -165,7 +165,7 @@ i9x5_scanout_layout(struct i915_texture *tex)
if (pt->width0 >= 240) {
tex->stride = get_pot_stride(pt->format, pt->width0);
tex->total_nblocksy = align_nblocksy(pt->format, pt->height0, 8);
tex->hw_tiled = I915_TILE_X;
tex->tiling = I915_TILE_X;
} else if (pt->width0 == 64 && pt->height0 == 64) {
tex->stride = get_pot_stride(pt->format, pt->width0);
tex->total_nblocksy = align_nblocksy(pt->format, pt->height0, 8);
@ -202,7 +202,7 @@ i9x5_display_target_layout(struct i915_texture *tex)
tex->stride = get_pot_stride(pt->format, pt->width0);
tex->total_nblocksy = align_nblocksy(pt->format, pt->height0, 8);
tex->hw_tiled = I915_TILE_X;
tex->tiling = I915_TILE_X;
#if DEBUG_TEXTURE
debug_printf("%s size: %d,%d,%d offset %d,%d (0x%x)\n", __FUNCTION__,
@ -790,8 +790,8 @@ i915_texture_create(struct pipe_screen *screen,
goto fail;
/* setup any hw fences */
if (tex->hw_tiled) {
iws->buffer_set_fence_reg(iws, tex->buffer, tex->stride, tex->hw_tiled);
if (tex->tiling) {
iws->buffer_set_fence_reg(iws, tex->buffer, tex->stride, tex->tiling);
}