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intel/isl: Support HIZ_CCS in emit_depth_stencil_hiz

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v2. Remove undocumented CCS_E-only mode for depth. (Nanley)

Co-authored-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2018-05-04 09:43:42 -07:00 • committed by Nanley Chery
parent 6312328a61
commit ab994ecae6
1 changed files with 10 additions and 2 deletions
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12
src/intel/isl/isl_emit_depth_stencil.c
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@ -109,6 +109,11 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
db.SurfaceQPitch =
isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2;
#endif
#if GEN_GEN >= 12
db.DepthBufferCompressionEnable =
info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS;
#endif
}
#if GEN_GEN == 5 || GEN_GEN == 6
@ -177,8 +182,11 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
};
assert(info->hiz_usage == ISL_AUX_USAGE_NONE ||
info->hiz_usage == ISL_AUX_USAGE_HIZ);
if (info->hiz_usage == ISL_AUX_USAGE_HIZ) {
info->hiz_usage == ISL_AUX_USAGE_HIZ ||
info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS);
if (info->hiz_usage == ISL_AUX_USAGE_HIZ ||
info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS) {
assert(GEN_GEN >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ);
db.HierarchicalDepthBufferEnable = true;
hiz.SurfaceBaseAddress = info->hiz_address;