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intel/blorp: Define the clear value bounds for HiZ clears

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Follow the restriction of making sure the clear value is between the min
and max values defined in CC_VIEWPORT. Avoids a simulator warning for
some piglit tests, one of them being:

./bin/depthstencil-render-miplevels 146 d=z32f_s8

Jason found this to fix incorrect clearing on SKL.

Fixes: 09948151ab
       ("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit 5bcf479524)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

Conflicts:
	src/intel/blorp/blorp_genX_exec.h
This commit is contained in:
Nanley Chery 2018-10-25 14:08:52 -07:00 • committed by Juan A. Suarez Romero
parent 8afef6d53a
commit aaff8c7a0e
1 changed files with 14 additions and 0 deletions
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14
src/intel/blorp/blorp_genX_exec.h
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@ -1637,6 +1637,20 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
*/
blorp_emit(batch, GENX(3DSTATE_WM), wm);
/* From the BDW PRM Volume 7, Depth Buffer Clear:
*
* The clear value must be between the min and max depth values
* (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
* D32_FLOAT, then +/-DENORM values are also allowed.
*
* Set the bounds to match our hardware limits, [0.0, 1.0].
*/
if (params->depth.enabled && params->hiz_op == ISL_AUX_OP_FAST_CLEAR) {
assert(params->depth.clear_color.f32[0] >= 0.0f);
assert(params->depth.clear_color.f32[0] <= 1.0f);
blorp_emit_cc_viewport(batch);
}
/* If we can't alter the depth stencil config and multiple layers are
* involved, the HiZ op will fail. This is because the op requires that a
* new config is emitted for each additional layer.