From aaf4d77f432f59902b53939bf0aee6f2121bbb02 Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Wed, 29 Apr 2026 14:13:07 +0200 Subject: [PATCH] ir3/shared_ra: fix live-out reload after src reload When reloading live-out values along loop back-edges, we make sure to reuse the original register. However, we failed to detect cases where the spilled value got reloaded earlier for a src in a different register. Fix this by reloading the value again in the original register. Fixes a RA validation failure in Windrose. Signed-off-by: Job Noorman Fixes: fa22b0901af ("ir3/ra: Add specialized shared register RA/spilling") Part-of: --- src/freedreno/ir3/ir3_shared_ra.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/freedreno/ir3/ir3_shared_ra.c b/src/freedreno/ir3/ir3_shared_ra.c index e90e63c85fb..58b2ba4fc67 100644 --- a/src/freedreno/ir3/ir3_shared_ra.c +++ b/src/freedreno/ir3/ir3_shared_ra.c @@ -1246,7 +1246,9 @@ reload_live_outs(struct ra_ctx *ctx, struct ir3_block *block) struct ir3_register *reg = ctx->live->definitions[name]; struct ra_interval *interval = &ctx->intervals[name]; - if (!interval->interval.inserted) { + if (!interval->interval.inserted || + (interval->spill_def && + interval->physreg_start != interval->physreg_start_orig)) { d("reloading %d at end of backedge", reg->name); /* When this interval was spilled inside the loop, we probably chose a