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panvk: Always set pan_fb_layout.rt_count to at least 1
Instead of having the pan_fb code have to `max(rt_count, 1)` add then constantly be doing the same in the driver, just make the condition an assert and do the `max(colorAttachmentCount, 1)` up-front. This way we're not constantly worried if everyone has the same count or not. The pan_fb code will handle having an empty render target just fine. Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com> Acked-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Eric R. Smith <eric.smith@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39759>
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7 changed files with 22 additions and 25 deletions
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@ -429,8 +429,6 @@ GENX(pan_emit_fb_desc)(const struct pan_fb_desc_info *info, void *out)
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const struct pan_fb_store *store = info->store;
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const bool has_zs_crc_ext = pan_fb_has_zs(fb);
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assert(fb->rt_count > 0 || fb->rt_formats[0] == PIPE_FORMAT_NONE);
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const unsigned rt_count = MAX2(fb->rt_count, 1);
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struct mali_framebuffer_packed fbd = {};
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@ -502,7 +500,8 @@ GENX(pan_emit_fb_desc)(const struct pan_fb_desc_info *info, void *out)
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cfg.first_provoking_vertex = info->provoking_vertex_first;
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#endif
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cfg.render_target_count = rt_count;
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assert(fb->rt_count > 0);
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cfg.render_target_count = fb->rt_count;
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cfg.color_buffer_allocation = fb->tile_rt_alloc_B;
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if (fb->s_format != PIPE_FORMAT_NONE) {
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@ -553,7 +552,7 @@ GENX(pan_emit_fb_desc)(const struct pan_fb_desc_info *info, void *out)
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}
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uint32_t tile_rt_offset_B = 0;
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for (unsigned rt = 0; rt < rt_count; rt++) {
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for (unsigned rt = 0; rt < fb->rt_count; rt++) {
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struct mali_rgb_render_target_packed rgb_rt;
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emit_rgb_rt_desc(info, rt, tile_rt_offset_B, &rgb_rt);
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memcpy(out, &rgb_rt, sizeof(rgb_rt));
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@ -569,7 +568,7 @@ GENX(pan_emit_fb_desc)(const struct pan_fb_desc_info *info, void *out)
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struct mali_framebuffer_pointer_packed tag;
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pan_pack(&tag, FRAMEBUFFER_POINTER, cfg) {
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cfg.zs_crc_extension_present = has_zs_crc_ext;
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cfg.render_target_count = rt_count;
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cfg.render_target_count = fb->rt_count;
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}
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return tag.opaque[0];
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}
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@ -133,9 +133,8 @@ calc_fn_set_fbds_provoking_vertex_idx(struct panvk_cmd_buffer *cmdbuf)
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{
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const struct pan_fb_layout *fb = &cmdbuf->state.gfx.render.fb.layout;
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const bool has_zs_ext = pan_fb_has_zs(fb);
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uint32_t rt_count = MAX2(fb->rt_count, 1);
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return get_fn_set_fbds_provoking_vertex_idx(has_zs_ext, rt_count);
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return get_fn_set_fbds_provoking_vertex_idx(has_zs_ext, fb->rt_count);
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}
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VkResult
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@ -663,7 +662,7 @@ prepare_blend(struct panvk_cmd_buffer *cmdbuf)
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const struct panvk_shader_variant *fs =
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panvk_shader_only_variant(get_fs(cmdbuf));
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uint32_t bd_count = MAX2(cmdbuf->state.gfx.render.fb.layout.rt_count, 1);
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uint32_t bd_count = cmdbuf->state.gfx.render.fb.layout.rt_count;
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struct cs_builder *b =
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panvk_get_cs_builder(cmdbuf, PANVK_SUBQUEUE_VERTEX_TILER);
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struct pan_ptr ptr = panvk_cmd_alloc_desc_array(cmdbuf, bd_count, BLEND);
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@ -927,9 +926,8 @@ calc_fbd_size(struct panvk_cmd_buffer *cmdbuf)
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{
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const struct pan_fb_layout *fb = &cmdbuf->state.gfx.render.fb.layout;
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const bool has_zs_ext = pan_fb_has_zs(fb);
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uint32_t rt_count = MAX2(fb->rt_count, 1);
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return get_fbd_size(has_zs_ext, rt_count);
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return get_fbd_size(has_zs_ext, fb->rt_count);
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}
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static uint32_t
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@ -1329,7 +1327,7 @@ get_fb_descs(struct panvk_cmd_buffer *cmdbuf)
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}
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const bool has_zs_ext = pan_fb_has_zs(&render->fb.layout);
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const uint32_t rt_count = MAX2(render->fb.layout.rt_count, 1);
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const uint32_t rt_count = render->fb.layout.rt_count;
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struct cs_builder *b = panvk_get_cs_builder(cmdbuf, PANVK_SUBQUEUE_FRAGMENT);
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for (uint32_t ir_pass = 0; ir_pass < PANVK_IR_PASS_COUNT; ir_pass++) {
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@ -2990,7 +2988,7 @@ panvk_per_arch(cmd_inherit_render_state)(
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render->fb.layout.sample_count == sample_count);
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render->fb.layout = (struct pan_fb_layout) {
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.sample_count = sample_count,
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.rt_count = inheritance_info->colorAttachmentCount,
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.rt_count = MAX2(inheritance_info->colorAttachmentCount, 1),
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.tile_size_px = render->fb.layout.tile_size_px,
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.tile_rt_alloc_B = render->fb.layout.tile_rt_alloc_B,
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@ -3324,9 +3322,8 @@ calc_tiler_oom_handler_idx(struct panvk_cmd_buffer *cmdbuf)
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{
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const struct pan_fb_layout *fb = &cmdbuf->state.gfx.render.fb.layout;
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const bool has_zs_ext = pan_fb_has_zs(fb);
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uint32_t rt_count = MAX2(fb->rt_count, 1);
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return get_tiler_oom_handler_idx(has_zs_ext, rt_count);
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return get_tiler_oom_handler_idx(has_zs_ext, fb->rt_count);
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}
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static void
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@ -3475,7 +3472,7 @@ issue_fragment_jobs(struct panvk_cmd_buffer *cmdbuf)
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}
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const bool has_zs_ext = pan_fb_has_zs(fb);
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const uint32_t rt_count = MAX2(fb->rt_count, 1);
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const uint32_t rt_count = fb->rt_count;
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/* IR was hit: set up IR FBD */
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cs_if(b, MALI_CS_CONDITION_GREATER, counter) {
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@ -214,7 +214,7 @@ panvk_per_arch(cmd_alloc_fb_desc)(struct panvk_cmd_buffer *cmdbuf)
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pan_size(ZS_CRC_EXTENSION);
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fbd_size = ALIGN_POT(fbd_size, pan_alignment(RENDER_TARGET)) +
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(MAX2(fb->rt_count, 1) * pan_size(RENDER_TARGET));
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(fb->rt_count * pan_size(RENDER_TARGET));
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batch->fb.bo_count = cmdbuf->state.gfx.render.fb.bo_count;
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memcpy(batch->fb.bos, cmdbuf->state.gfx.render.fb.bos,
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@ -241,7 +241,7 @@ panvk_draw_prepare_fs_rsd(struct panvk_cmd_buffer *cmdbuf,
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const struct panvk_shader_variant *fs =
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panvk_shader_only_variant(get_fs(cmdbuf));
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const struct pan_shader_info *fs_info = fs ? &fs->info : NULL;
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uint32_t bd_count = MAX2(cmdbuf->state.gfx.render.fb.layout.rt_count, 1);
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uint32_t bd_count = cmdbuf->state.gfx.render.fb.layout.rt_count;
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bool test_s = has_stencil_att(cmdbuf) && ds->stencil.test_enable;
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bool test_z = has_depth_att(cmdbuf) && ds->depth.test_enable;
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bool writes_z = writes_depth(cmdbuf);
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@ -296,7 +296,6 @@ panvk_per_arch(blend_emit_descs)(struct panvk_cmd_buffer *cmdbuf,
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uint64_t blend_shaders[8] = {};
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/* All bits set to one encodes unused fixed-function blend constant. */
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unsigned ff_blend_constant = ~0;
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uint32_t blend_count = MAX2(cmdbuf->state.gfx.render.fb.layout.rt_count, 1);
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uint8_t loc_rt[MAX_RTS], rt_loc[MAX_RTS];
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memset(loc_rt, MESA_VK_ATTACHMENT_UNUSED, sizeof(loc_rt));
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@ -380,13 +379,13 @@ panvk_per_arch(blend_emit_descs)(struct panvk_cmd_buffer *cmdbuf,
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ff_blend_constant = 0;
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struct mali_blend_packed packed[MAX_RTS];
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for (uint8_t rt = 0; rt < blend_count; rt++) {
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for (uint8_t rt = 0; rt < bs.rt_count; rt++) {
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emit_blend_desc(&bs, rt, fs_info, rt_loc[rt], fs_code,
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blend_shaders[rt], ff_blend_constant, &packed[rt]);
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}
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/* Copy into the GPU descriptor array */
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typed_memcpy(bds, packed, blend_count);
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typed_memcpy(bds, packed, bs.rt_count);
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/* Re-order blend descriptors for the shader
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*
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@ -471,7 +471,11 @@ panvk_per_arch(cmd_init_render_state)(struct panvk_cmd_buffer *cmdbuf,
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* value if we don't set it here already.
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*/
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.sample_count = 0,
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.rt_count = pRenderingInfo->colorAttachmentCount,
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/* The hardware requires us to have at least one color target, even if
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* it's a dummy.
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*/
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.rt_count = MAX2(pRenderingInfo->colorAttachmentCount, 1),
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.tile_rt_budget_B =
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pan_query_optimal_tib_size(PAN_ARCH, phys_dev->model),
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@ -349,9 +349,7 @@ fill_bds(const struct pan_fb_layout *fb,
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const struct panvk_fb_preload_shader_key *key,
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struct mali_blend_packed *bds)
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{
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uint32_t bd_count = MAX2(fb->rt_count, 1);
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for (unsigned i = 0; i < bd_count; i++) {
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for (unsigned i = 0; i < fb->rt_count; i++) {
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pan_pack(&bds[i], BLEND, cfg) {
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if (!pan_fb_shader_key_target_written(&key->key.rts[i]) ||
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fb->rt_formats[i] == PIPE_FORMAT_NONE) {
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@ -421,7 +419,7 @@ cmd_emit_dcd(struct panvk_cmd_buffer *cmdbuf,
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assert(preload_color != (preload_z || preload_s));
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uint32_t tex_count = util_bitcount(locations_written);
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uint32_t bd_count = MAX2(fb->rt_count, 1);
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uint32_t bd_count = fb->rt_count;
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struct pan_ptr rsd = panvk_cmd_alloc_desc_aggregate(
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cmdbuf, PAN_DESC(RENDERER_STATE),
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