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freedreno: use autogenerated register defs
Switch to use the envytools generated headers for register/bitfield definitions. This is the first step in preparing to add a3xx support, since it avoids having conflicting names for a3xx and a2xx registers. And since I'm using envytools for a3xx it is simpler to just use it for everything. This shouldn't cause any functional change, it is really just a lot of renaming. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
1fefc65d20
commit
aac7f06ad8
23 changed files with 2116 additions and 1617 deletions
1473
src/gallium/drivers/freedreno/a2xx.xml.h
Normal file
1473
src/gallium/drivers/freedreno/a2xx.xml.h
Normal file
File diff suppressed because it is too large
Load diff
112
src/gallium/drivers/freedreno/adreno_common.xml.h
Normal file
112
src/gallium/drivers/freedreno/adreno_common.xml.h
Normal file
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@ -0,0 +1,112 @@
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#ifndef ADRENO_COMMON_XML
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#define ADRENO_COMMON_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
|
||||
http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
|
||||
- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 35685 bytes, from 2013-04-05 17:33:03)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 2972 bytes, from 2013-04-05 17:32:38)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 7736 bytes, from 2013-04-04 20:24:12)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
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||||
|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
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LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
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OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum adreno_pa_su_sc_draw {
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PC_DRAW_POINTS = 0,
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PC_DRAW_LINES = 1,
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PC_DRAW_TRIANGLES = 2,
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};
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enum adreno_compare_func {
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FUNC_NEVER = 0,
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FUNC_LESS = 1,
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FUNC_EQUAL = 2,
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FUNC_LEQUAL = 3,
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FUNC_GREATER = 4,
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FUNC_NOTEQUAL = 5,
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FUNC_GEQUAL = 6,
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FUNC_ALWAYS = 7,
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};
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enum adreno_stencil_op {
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STENCIL_KEEP = 0,
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STENCIL_ZERO = 1,
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STENCIL_REPLACE = 2,
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STENCIL_INCR_CLAMP = 3,
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STENCIL_DECR_CLAMP = 4,
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STENCIL_INVERT = 5,
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STENCIL_INCR_WRAP = 6,
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STENCIL_DECR_WRAP = 7,
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};
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enum adreno_rb_blend_factor {
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FACTOR_ZERO = 0,
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FACTOR_ONE = 1,
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FACTOR_SRC_COLOR = 4,
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FACTOR_ONE_MINUS_SRC_COLOR = 5,
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FACTOR_SRC_ALPHA = 6,
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FACTOR_ONE_MINUS_SRC_ALPHA = 7,
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FACTOR_DST_COLOR = 8,
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FACTOR_ONE_MINUS_DST_COLOR = 9,
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FACTOR_DST_ALPHA = 10,
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FACTOR_ONE_MINUS_DST_ALPHA = 11,
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FACTOR_CONSTANT_COLOR = 12,
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FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
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FACTOR_CONSTANT_ALPHA = 14,
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FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
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FACTOR_SRC_ALPHA_SATURATE = 16,
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};
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enum adreno_rb_blend_opcode {
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BLEND_DST_PLUS_SRC = 0,
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BLEND_SRC_MINUS_DST = 1,
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BLEND_MIN_DST_SRC = 2,
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BLEND_MAX_DST_SRC = 3,
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BLEND_DST_MINUS_SRC = 4,
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BLEND_DST_PLUS_SRC_BIAS = 5,
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};
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enum adreno_rb_surface_endian {
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ENDIAN_NONE = 0,
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ENDIAN_8IN16 = 1,
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ENDIAN_8IN32 = 2,
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ENDIAN_16IN32 = 3,
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ENDIAN_8IN64 = 4,
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ENDIAN_8IN128 = 5,
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};
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enum adreno_rb_dither_mode {
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DITHER_DISABLE = 0,
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DITHER_ALWAYS = 1,
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DITHER_IF_ALPHA_OFF = 2,
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};
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#endif /* ADRENO_COMMON_XML */
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160
src/gallium/drivers/freedreno/adreno_pm4.xml.h
Normal file
160
src/gallium/drivers/freedreno/adreno_pm4.xml.h
Normal file
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@ -0,0 +1,160 @@
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#ifndef ADRENO_PM4_XML
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#define ADRENO_PM4_XML
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/* Autogenerated file, DO NOT EDIT manually!
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This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://0x04.net/cgit/index.cgi/rules-ng-ng
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git clone git://0x04.net/rules-ng-ng
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml ( 35685 bytes, from 2013-04-05 17:33:03)
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- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 2972 bytes, from 2013-04-05 17:32:38)
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- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 7736 bytes, from 2013-04-04 20:24:12)
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Copyright (C) 2013 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
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The above copyright notice and this permission notice (including the
|
||||
next paragraph) shall be included in all copies or substantial
|
||||
portions of the Software.
|
||||
|
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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enum vgt_event_type {
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VS_DEALLOC = 0,
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PS_DEALLOC = 1,
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VS_DONE_TS = 2,
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PS_DONE_TS = 3,
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CACHE_FLUSH_TS = 4,
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CONTEXT_DONE = 5,
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CACHE_FLUSH = 6,
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VIZQUERY_START = 7,
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VIZQUERY_END = 8,
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SC_WAIT_WC = 9,
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RST_PIX_CNT = 13,
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RST_VTX_CNT = 14,
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TILE_FLUSH = 15,
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CACHE_FLUSH_AND_INV_TS_EVENT = 20,
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ZPASS_DONE = 21,
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CACHE_FLUSH_AND_INV_EVENT = 22,
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PERFCOUNTER_START = 23,
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PERFCOUNTER_STOP = 24,
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VS_FETCH_DONE = 27,
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FACENESS_FLUSH = 28,
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};
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enum pc_di_primtype {
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DI_PT_NONE = 0,
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DI_PT_POINTLIST = 1,
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DI_PT_LINELIST = 2,
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DI_PT_LINESTRIP = 3,
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DI_PT_TRILIST = 4,
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DI_PT_TRIFAN = 5,
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DI_PT_TRISTRIP = 6,
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DI_PT_RECTLIST = 8,
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DI_PT_QUADLIST = 13,
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DI_PT_QUADSTRIP = 14,
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DI_PT_POLYGON = 15,
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DI_PT_2D_COPY_RECT_LIST_V0 = 16,
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DI_PT_2D_COPY_RECT_LIST_V1 = 17,
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DI_PT_2D_COPY_RECT_LIST_V2 = 18,
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DI_PT_2D_COPY_RECT_LIST_V3 = 19,
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DI_PT_2D_FILL_RECT_LIST = 20,
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DI_PT_2D_LINE_STRIP = 21,
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DI_PT_2D_TRI_STRIP = 22,
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};
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enum pc_di_src_sel {
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DI_SRC_SEL_DMA = 0,
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DI_SRC_SEL_IMMEDIATE = 1,
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DI_SRC_SEL_AUTO_INDEX = 2,
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DI_SRC_SEL_RESERVED = 3,
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};
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enum pc_di_index_size {
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INDEX_SIZE_IGN = 0,
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INDEX_SIZE_16_BIT = 0,
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INDEX_SIZE_32_BIT = 1,
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INDEX_SIZE_8_BIT = 2,
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INDEX_SIZE_INVALID = 0,
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};
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enum pc_di_vis_cull_mode {
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IGNORE_VISIBILITY = 0,
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};
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enum adreno_pm4_packet_type {
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CP_TYPE0_PKT = 0,
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CP_TYPE1_PKT = 0x40000000,
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CP_TYPE2_PKT = 0x80000000,
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CP_TYPE3_PKT = 0xc0000000,
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};
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enum adreno_pm4_type3_packets {
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CP_ME_INIT = 72,
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CP_NOP = 16,
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CP_INDIRECT_BUFFER = 63,
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CP_INDIRECT_BUFFER_PFD = 55,
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CP_WAIT_FOR_IDLE = 38,
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CP_WAIT_REG_MEM = 60,
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CP_WAIT_REG_EQ = 82,
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CP_WAT_REG_GTE = 83,
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CP_WAIT_UNTIL_READ = 92,
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CP_WAIT_IB_PFD_COMPLETE = 93,
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CP_REG_RMW = 33,
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CP_SET_BIN_DATA = 47,
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CP_REG_TO_MEM = 62,
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CP_MEM_WRITE = 61,
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CP_MEM_WRITE_CNTR = 79,
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CP_COND_EXEC = 68,
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CP_COND_WRITE = 69,
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CP_EVENT_WRITE = 70,
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CP_EVENT_WRITE_SHD = 88,
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CP_EVENT_WRITE_CFL = 89,
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CP_EVENT_WRITE_ZPD = 91,
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CP_DRAW_INDX = 34,
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CP_DRAW_INDX_2 = 54,
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CP_DRAW_INDX_BIN = 52,
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CP_DRAW_INDX_2_BIN = 53,
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CP_VIZ_QUERY = 35,
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CP_SET_STATE = 37,
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CP_SET_CONSTANT = 45,
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CP_IM_LOAD = 39,
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CP_IM_LOAD_IMMEDIATE = 43,
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CP_LOAD_CONSTANT_CONTEXT = 46,
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CP_INVALIDATE_STATE = 59,
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CP_SET_SHADER_BASES = 74,
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CP_SET_BIN_MASK = 80,
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CP_SET_BIN_SELECT = 81,
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CP_CONTEXT_UPDATE = 94,
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CP_INTERRUPT = 64,
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CP_IM_STORE = 44,
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CP_SET_BIN_BASE_OFFSET = 75,
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CP_SET_DRAW_INIT_FLAGS = 75,
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CP_SET_PROTECTED_MODE = 95,
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CP_LOAD_STATE = 48,
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CP_COND_INDIRECT_BUFFER_PFE = 58,
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CP_COND_INDIRECT_BUFFER_PFD = 50,
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CP_INDIRECT_BUFFER_PFE = 63,
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};
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#endif /* ADRENO_PM4_XML */
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@ -31,7 +31,7 @@
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#include <string.h>
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#include "disasm.h"
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#include "instr.h"
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#include "instr-a2xx.h"
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static const char *levels[] = {
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"\t",
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File diff suppressed because it is too large
Load diff
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@ -34,41 +34,41 @@
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#include "freedreno_context.h"
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#include "freedreno_util.h"
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static enum rb_blend_op
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static enum adreno_rb_blend_factor
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blend_factor(unsigned factor)
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{
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switch (factor) {
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case PIPE_BLENDFACTOR_ONE:
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return RB_BLEND_ONE;
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return FACTOR_ONE;
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case PIPE_BLENDFACTOR_SRC_COLOR:
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return RB_BLEND_SRC_COLOR;
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return FACTOR_SRC_COLOR;
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case PIPE_BLENDFACTOR_SRC_ALPHA:
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return RB_BLEND_SRC_ALPHA;
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return FACTOR_SRC_ALPHA;
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case PIPE_BLENDFACTOR_DST_ALPHA:
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return RB_BLEND_DST_ALPHA;
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return FACTOR_DST_ALPHA;
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case PIPE_BLENDFACTOR_DST_COLOR:
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return RB_BLEND_DST_COLOR;
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return FACTOR_DST_COLOR;
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case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
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return RB_BLEND_SRC_ALPHA_SATURATE;
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return FACTOR_SRC_ALPHA_SATURATE;
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case PIPE_BLENDFACTOR_CONST_COLOR:
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return RB_BLEND_CONSTANT_COLOR;
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return FACTOR_CONSTANT_COLOR;
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case PIPE_BLENDFACTOR_CONST_ALPHA:
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return RB_BLEND_CONSTANT_ALPHA;
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return FACTOR_CONSTANT_ALPHA;
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case PIPE_BLENDFACTOR_ZERO:
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case 0:
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return RB_BLEND_ZERO;
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return FACTOR_ZERO;
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case PIPE_BLENDFACTOR_INV_SRC_COLOR:
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return RB_BLEND_ONE_MINUS_SRC_COLOR;
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return FACTOR_ONE_MINUS_SRC_COLOR;
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case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
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return RB_BLEND_ONE_MINUS_SRC_ALPHA;
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return FACTOR_ONE_MINUS_SRC_ALPHA;
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case PIPE_BLENDFACTOR_INV_DST_ALPHA:
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return RB_BLEND_ONE_MINUS_DST_ALPHA;
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return FACTOR_ONE_MINUS_DST_ALPHA;
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case PIPE_BLENDFACTOR_INV_DST_COLOR:
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return RB_BLEND_ONE_MINUS_DST_COLOR;
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return FACTOR_ONE_MINUS_DST_COLOR;
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case PIPE_BLENDFACTOR_INV_CONST_COLOR:
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return RB_BLEND_ONE_MINUS_CONSTANT_COLOR;
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return FACTOR_ONE_MINUS_CONSTANT_COLOR;
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case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
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return RB_BLEND_ONE_MINUS_CONSTANT_ALPHA;
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return FACTOR_ONE_MINUS_CONSTANT_ALPHA;
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case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
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case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
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case PIPE_BLENDFACTOR_SRC1_COLOR:
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@ -80,20 +80,20 @@ blend_factor(unsigned factor)
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}
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}
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static enum rb_comb_func
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static enum adreno_rb_blend_opcode
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blend_func(unsigned func)
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{
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switch (func) {
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case PIPE_BLEND_ADD:
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return COMB_DST_PLUS_SRC;
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return BLEND_DST_PLUS_SRC;
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case PIPE_BLEND_MIN:
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return COMB_MIN_DST_SRC;
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return BLEND_MIN_DST_SRC;
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case PIPE_BLEND_MAX:
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return COMB_MAX_DST_SRC;
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return BLEND_MAX_DST_SRC;
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case PIPE_BLEND_SUBTRACT:
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return COMB_SRC_MINUS_DST;
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return BLEND_SRC_MINUS_DST;
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case PIPE_BLEND_REVERSE_SUBTRACT:
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return COMB_DST_MINUS_SRC;
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return BLEND_DST_MINUS_SRC;
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default:
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DBG("invalid blend func: %x", func);
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return 0;
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@ -123,30 +123,30 @@ fd_blend_state_create(struct pipe_context *pctx,
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so->base = *cso;
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so->rb_colorcontrol = RB_COLORCONTROL_ROP_CODE(12);
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so->rb_colorcontrol = A2XX_RB_COLORCONTROL_ROP_CODE(12);
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so->rb_blendcontrol =
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RB_BLENDCONTROL_COLOR_SRCBLEND(blend_factor(rt->rgb_src_factor)) |
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RB_BLENDCONTROL_COLOR_COMB_FCN(blend_func(rt->rgb_func)) |
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RB_BLENDCONTROL_COLOR_DESTBLEND(blend_factor(rt->rgb_dst_factor)) |
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RB_BLENDCONTROL_ALPHA_SRCBLEND(blend_factor(rt->alpha_src_factor)) |
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RB_BLENDCONTROL_ALPHA_COMB_FCN(blend_func(rt->alpha_func)) |
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RB_BLENDCONTROL_ALPHA_DESTBLEND(blend_factor(rt->alpha_dst_factor));
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A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(blend_factor(rt->rgb_src_factor)) |
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A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(blend_func(rt->rgb_func)) |
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A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(blend_factor(rt->rgb_dst_factor)) |
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A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(blend_factor(rt->alpha_src_factor)) |
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A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(blend_func(rt->alpha_func)) |
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A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(blend_factor(rt->alpha_dst_factor));
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if (rt->colormask & PIPE_MASK_R)
|
||||
so->rb_colormask |= RB_COLOR_MASK_WRITE_RED;
|
||||
so->rb_colormask |= A2XX_RB_COLOR_MASK_WRITE_RED;
|
||||
if (rt->colormask & PIPE_MASK_G)
|
||||
so->rb_colormask |= RB_COLOR_MASK_WRITE_GREEN;
|
||||
so->rb_colormask |= A2XX_RB_COLOR_MASK_WRITE_GREEN;
|
||||
if (rt->colormask & PIPE_MASK_B)
|
||||
so->rb_colormask |= RB_COLOR_MASK_WRITE_BLUE;
|
||||
so->rb_colormask |= A2XX_RB_COLOR_MASK_WRITE_BLUE;
|
||||
if (rt->colormask & PIPE_MASK_A)
|
||||
so->rb_colormask |= RB_COLOR_MASK_WRITE_ALPHA;
|
||||
so->rb_colormask |= A2XX_RB_COLOR_MASK_WRITE_ALPHA;
|
||||
|
||||
if (!rt->blend_enable)
|
||||
so->rb_colorcontrol |= RB_COLORCONTROL_BLEND_DISABLE;
|
||||
so->rb_colorcontrol |= A2XX_RB_COLORCONTROL_BLEND_DISABLE;
|
||||
|
||||
if (cso->dither)
|
||||
so->rb_colorcontrol |= RB_COLORCONTROL_DITHER_MODE(DITHER_ALWAYS);
|
||||
so->rb_colorcontrol |= A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_ALWAYS);
|
||||
|
||||
return so;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -82,48 +82,48 @@ fd_clear(struct pipe_context *pctx, unsigned buffers,
|
|||
}, 1);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, 0);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, 0x0000028f);
|
||||
|
||||
fd_program_emit(ring, &ctx->solid_prog);
|
||||
|
||||
OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1);
|
||||
OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE);
|
||||
OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
|
||||
OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_CLEAR_COLOR));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_CLEAR_COLOR));
|
||||
OUT_RING(ring, colr);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_A220_RB_LRZ_VSC_CONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
|
||||
OUT_RING(ring, 0x00000084);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
|
||||
reg = 0;
|
||||
if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
|
||||
reg |= RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
|
||||
reg |= A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
|
||||
switch (fd_pipe2depth(fb->zsbuf->format)) {
|
||||
case DEPTHX_24_8:
|
||||
if (buffers & PIPE_CLEAR_DEPTH)
|
||||
reg |= RB_COPY_CONTROL_CLEAR_MASK(0xe);
|
||||
reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xe);
|
||||
if (buffers & PIPE_CLEAR_STENCIL)
|
||||
reg |= RB_COPY_CONTROL_CLEAR_MASK(0x1);
|
||||
reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0x1);
|
||||
break;
|
||||
case DEPTHX_16:
|
||||
if (buffers & PIPE_CLEAR_DEPTH)
|
||||
reg |= RB_COPY_CONTROL_CLEAR_MASK(0xf);
|
||||
reg |= A2XX_RB_COPY_CONTROL_CLEAR_MASK(0xf);
|
||||
break;
|
||||
}
|
||||
}
|
||||
OUT_RING(ring, reg);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_DEPTH_CLEAR));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTH_CLEAR));
|
||||
reg = 0;
|
||||
if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
|
||||
switch (fd_pipe2depth(fb->zsbuf->format)) {
|
||||
|
|
@ -139,45 +139,45 @@ fd_clear(struct pipe_context *pctx, unsigned buffers,
|
|||
OUT_RING(ring, reg);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
|
||||
reg = 0;
|
||||
if (buffers & PIPE_CLEAR_DEPTH) {
|
||||
reg |= RB_DEPTHCONTROL_ZFUNC(GL_ALWAYS) |
|
||||
RB_DEPTHCONTROL_Z_ENABLE |
|
||||
RB_DEPTHCONTROL_Z_WRITE_ENABLE |
|
||||
RB_DEPTHCONTROL_EARLY_Z_ENABLE;
|
||||
reg |= A2XX_RB_DEPTHCONTROL_ZFUNC(FUNC_ALWAYS) |
|
||||
A2XX_RB_DEPTHCONTROL_Z_ENABLE |
|
||||
A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE |
|
||||
A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE;
|
||||
}
|
||||
if (buffers & PIPE_CLEAR_STENCIL) {
|
||||
reg |= RB_DEPTHCONTROL_STENCILFUNC(GL_ALWAYS) |
|
||||
RB_DEPTHCONTROL_STENCIL_ENABLE |
|
||||
RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
|
||||
reg |= A2XX_RB_DEPTHCONTROL_STENCILFUNC(FUNC_ALWAYS) |
|
||||
A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
|
||||
A2XX_RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
|
||||
}
|
||||
OUT_RING(ring, reg);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
|
||||
OUT_RING(ring, 0x00000000); /* PA_CL_CLIP_CNTL */
|
||||
OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */
|
||||
PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) |
|
||||
PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES));
|
||||
OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */
|
||||
A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
|
||||
A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
|
||||
OUT_RING(ring, 0x0000ffff);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
|
||||
OUT_RING(ring, xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
|
||||
OUT_RING(ring, xy2d(fb->width, /* PA_SC_WINDOW_SCISSOR_BR */
|
||||
fb->height));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLOR_MASK));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
|
||||
if (buffers & PIPE_CLEAR_COLOR) {
|
||||
OUT_RING(ring, RB_COLOR_MASK_WRITE_RED |
|
||||
RB_COLOR_MASK_WRITE_GREEN |
|
||||
RB_COLOR_MASK_WRITE_BLUE |
|
||||
RB_COLOR_MASK_WRITE_ALPHA);
|
||||
OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
|
||||
A2XX_RB_COLOR_MASK_WRITE_GREEN |
|
||||
A2XX_RB_COLOR_MASK_WRITE_BLUE |
|
||||
A2XX_RB_COLOR_MASK_WRITE_ALPHA);
|
||||
} else {
|
||||
OUT_RING(ring, 0x0);
|
||||
}
|
||||
|
|
@ -189,11 +189,11 @@ fd_clear(struct pipe_context *pctx, unsigned buffers,
|
|||
OUT_RING(ring, 3); /* NumIndices */
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_A220_RB_LRZ_VSC_CONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
ctx->dirty |= FD_DIRTY_ZSA |
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
#include "freedreno_compiler.h"
|
||||
#include "freedreno_util.h"
|
||||
|
||||
#include "instr.h"
|
||||
#include "instr-a2xx.h"
|
||||
#include "ir.h"
|
||||
|
||||
struct fd_compile_context {
|
||||
|
|
@ -875,10 +875,10 @@ translate_sge_slt(struct fd_compile_context *ctx,
|
|||
* in assembler/disassembler and what ir.c expects
|
||||
* is: MULADDv Rdst = Rsrc2 + Rsrc0 * Rscr1
|
||||
*/
|
||||
get_immediate(ctx, &tmp_const, f2d(c0));
|
||||
get_immediate(ctx, &tmp_const, fui(c0));
|
||||
add_src_reg(ctx, instr, &tmp_const);
|
||||
add_src_reg(ctx, instr, &tmp_src);
|
||||
get_immediate(ctx, &tmp_const, f2d(c1));
|
||||
get_immediate(ctx, &tmp_const, fui(c1));
|
||||
add_src_reg(ctx, instr, &tmp_const);
|
||||
}
|
||||
|
||||
|
|
@ -896,7 +896,7 @@ translate_lrp(struct fd_compile_context *ctx,
|
|||
get_internal_temp(ctx, &inst->Dst[0].Register, &tmp_dst1, &tmp_src1);
|
||||
get_internal_temp(ctx, NULL, &tmp_dst2, &tmp_src2);
|
||||
|
||||
get_immediate(ctx, &tmp_const, f2d(1.0));
|
||||
get_immediate(ctx, &tmp_const, fui(1.0));
|
||||
|
||||
/* tmp1 = (a * b) */
|
||||
instr = ir_instr_create_alu(next_exec_cf(ctx), MULv, ~0);
|
||||
|
|
@ -957,10 +957,10 @@ translate_trig(struct fd_compile_context *ctx,
|
|||
*/
|
||||
instr = ir_instr_create_alu(next_exec_cf(ctx), MULADDv, ~0);
|
||||
add_dst_reg(ctx, instr, &tmp_dst);
|
||||
get_immediate(ctx, &tmp_const, f2d(0.5));
|
||||
get_immediate(ctx, &tmp_const, fui(0.5));
|
||||
add_src_reg(ctx, instr, &tmp_const);
|
||||
add_src_reg(ctx, instr, &inst->Src[0].Register);
|
||||
get_immediate(ctx, &tmp_const, f2d(0.159155));
|
||||
get_immediate(ctx, &tmp_const, fui(0.159155));
|
||||
add_src_reg(ctx, instr, &tmp_const);
|
||||
|
||||
instr = ir_instr_create_alu(next_exec_cf(ctx), FRACv, ~0);
|
||||
|
|
@ -970,10 +970,10 @@ translate_trig(struct fd_compile_context *ctx,
|
|||
|
||||
instr = ir_instr_create_alu(next_exec_cf(ctx), MULADDv, ~0);
|
||||
add_dst_reg(ctx, instr, &tmp_dst);
|
||||
get_immediate(ctx, &tmp_const, f2d(-3.141593));
|
||||
get_immediate(ctx, &tmp_const, fui(-3.141593));
|
||||
add_src_reg(ctx, instr, &tmp_const);
|
||||
add_src_reg(ctx, instr, &tmp_src);
|
||||
get_immediate(ctx, &tmp_const, f2d(6.283185));
|
||||
get_immediate(ctx, &tmp_const, fui(6.283185));
|
||||
add_src_reg(ctx, instr, &tmp_const);
|
||||
|
||||
instr = ir_instr_create_alu(next_exec_cf(ctx), ~0, op);
|
||||
|
|
|
|||
|
|
@ -78,23 +78,24 @@ emit_gmem2mem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
|
|||
struct fd_resource *rsc = fd_resource(psurf->texture);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO));
|
||||
OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(swap) |
|
||||
RB_COLOR_INFO_COLOR_BASE(base / 1024) |
|
||||
RB_COLOR_INFO_COLOR_FORMAT(fd_pipe2color(psurf->format)));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
|
||||
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
|
||||
A2XX_RB_COLOR_INFO_BASE(base / 1024) |
|
||||
A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf->format)));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
|
||||
OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */
|
||||
OUT_RELOC(ring, rsc->bo, 0, 0); /* RB_COPY_DEST_BASE */
|
||||
OUT_RING(ring, rsc->pitch >> 5); /* RB_COPY_DEST_PITCH */
|
||||
OUT_RING(ring, RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf->format)) |
|
||||
RB_COPY_DEST_INFO_LINEAR | /* RB_COPY_DEST_INFO */
|
||||
RB_COPY_DEST_INFO_SWAP(swap) |
|
||||
RB_COPY_DEST_INFO_WRITE_RED |
|
||||
RB_COPY_DEST_INFO_WRITE_GREEN |
|
||||
RB_COPY_DEST_INFO_WRITE_BLUE |
|
||||
RB_COPY_DEST_INFO_WRITE_ALPHA);
|
||||
OUT_RING(ring, /* RB_COPY_DEST_INFO */
|
||||
A2XX_RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf->format)) |
|
||||
A2XX_RB_COPY_DEST_INFO_LINEAR |
|
||||
A2XX_RB_COPY_DEST_INFO_SWAP(swap) |
|
||||
A2XX_RB_COPY_DEST_INFO_WRITE_RED |
|
||||
A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
|
||||
A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
|
||||
A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
|
||||
|
||||
OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
|
||||
OUT_RING(ring, 0x0000000);
|
||||
|
|
@ -117,53 +118,54 @@ emit_gmem2mem(struct fd_context *ctx, struct fd_ringbuffer *ring,
|
|||
}, 1);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, 0);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, 0x0000028f);
|
||||
|
||||
fd_program_emit(ring, &ctx->solid_prog);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
|
||||
OUT_RING(ring, 0x0000ffff);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
|
||||
OUT_RING(ring, RB_DEPTHCONTROL_EARLY_Z_ENABLE);
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
|
||||
OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SU_SC_MODE_CNTL));
|
||||
OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */
|
||||
PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) |
|
||||
PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
|
||||
OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST | /* PA_SU_SC_MODE_CNTL */
|
||||
A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
|
||||
A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
|
||||
OUT_RING(ring, xy2d(0, 0)); /* PA_SC_WINDOW_SCISSOR_TL */
|
||||
OUT_RING(ring, xy2d(pfb->width, pfb->height)); /* PA_SC_WINDOW_SCISSOR_BR */
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL));
|
||||
OUT_RING(ring, PA_CL_VTE_CNTL_VTX_W0_FMT |
|
||||
PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
|
||||
OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_MODECONTROL));
|
||||
OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
|
||||
OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COPY_DEST_OFFSET));
|
||||
OUT_RING(ring, RB_COPY_DEST_OFFSET_X(xoff) | RB_COPY_DEST_OFFSET_Y(yoff));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET));
|
||||
OUT_RING(ring, A2XX_RB_COPY_DEST_OFFSET_X(xoff) |
|
||||
A2XX_RB_COPY_DEST_OFFSET_Y(yoff));
|
||||
|
||||
if (ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
|
||||
emit_gmem2mem_surf(ring, 0, bin_w * bin_h, pfb->zsbuf);
|
||||
|
|
@ -172,8 +174,8 @@ emit_gmem2mem(struct fd_context *ctx, struct fd_ringbuffer *ring,
|
|||
emit_gmem2mem_surf(ring, 1, 0, pfb->cbufs[0]);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_MODECONTROL));
|
||||
OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
|
||||
OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
|
||||
}
|
||||
|
||||
/* transfer from system memory to gmem */
|
||||
|
|
@ -186,10 +188,10 @@ emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
|
|||
uint32_t swiz;
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO));
|
||||
OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(swap) |
|
||||
RB_COLOR_INFO_COLOR_BASE(base / 1024) |
|
||||
RB_COLOR_INFO_COLOR_FORMAT(fd_pipe2color(psurf->format)));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
|
||||
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
|
||||
A2XX_RB_COLOR_INFO_BASE(base) |
|
||||
A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf->format)));
|
||||
|
||||
swiz = fd_tex_swiz(psurf->format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
|
||||
PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA);
|
||||
|
|
@ -197,18 +199,18 @@ emit_mem2gmem_surf(struct fd_ringbuffer *ring, uint32_t swap, uint32_t base,
|
|||
/* emit fb as a texture: */
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 7);
|
||||
OUT_RING(ring, 0x00010000);
|
||||
OUT_RING(ring, SQ_TEX0_CLAMP_X(SQ_TEX_WRAP) |
|
||||
SQ_TEX0_CLAMP_Y(SQ_TEX_WRAP) |
|
||||
SQ_TEX0_CLAMP_Z(SQ_TEX_WRAP) |
|
||||
SQ_TEX0_PITCH(rsc->pitch));
|
||||
OUT_RING(ring, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP) |
|
||||
A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP) |
|
||||
A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP) |
|
||||
A2XX_SQ_TEX_0_PITCH(rsc->pitch));
|
||||
OUT_RELOC(ring, rsc->bo, 0,
|
||||
fd_pipe2surface(psurf->format) | 0x800);
|
||||
OUT_RING(ring, SQ_TEX2_WIDTH(psurf->width) |
|
||||
SQ_TEX2_HEIGHT(psurf->height));
|
||||
OUT_RING(ring, A2XX_SQ_TEX_2_WIDTH(psurf->width - 1) |
|
||||
A2XX_SQ_TEX_2_HEIGHT(psurf->height - 1));
|
||||
OUT_RING(ring, 0x01000000 | // XXX
|
||||
swiz |
|
||||
SQ_TEX3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
|
||||
SQ_TEX3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
|
||||
A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT) |
|
||||
A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
OUT_RING(ring, 0x00000200);
|
||||
|
||||
|
|
@ -238,83 +240,83 @@ emit_mem2gmem(struct fd_context *ctx, struct fd_ringbuffer *ring,
|
|||
y1 = ((float)yoff + bin_h) / ((float)pfb->height);
|
||||
OUT_PKT3(ring, CP_MEM_WRITE, 9);
|
||||
OUT_RELOC(ring, fd_resource(ctx->solid_vertexbuf)->bo, 0x60, 0);
|
||||
OUT_RING(ring, f2d(x0));
|
||||
OUT_RING(ring, f2d(y0));
|
||||
OUT_RING(ring, f2d(x1));
|
||||
OUT_RING(ring, f2d(y0));
|
||||
OUT_RING(ring, f2d(x0));
|
||||
OUT_RING(ring, f2d(y1));
|
||||
OUT_RING(ring, f2d(x1));
|
||||
OUT_RING(ring, f2d(y1));
|
||||
OUT_RING(ring, fui(x0));
|
||||
OUT_RING(ring, fui(y0));
|
||||
OUT_RING(ring, fui(x1));
|
||||
OUT_RING(ring, fui(y0));
|
||||
OUT_RING(ring, fui(x0));
|
||||
OUT_RING(ring, fui(y1));
|
||||
OUT_RING(ring, fui(x1));
|
||||
OUT_RING(ring, fui(y1));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, 0);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, 0x0000003b);
|
||||
|
||||
fd_program_emit(ring, &ctx->blit_prog);
|
||||
|
||||
OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1);
|
||||
OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE);
|
||||
OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
|
||||
OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
|
||||
OUT_RING(ring, RB_DEPTHCONTROL_EARLY_Z_ENABLE);
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
|
||||
OUT_RING(ring, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SU_SC_MODE_CNTL));
|
||||
OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
|
||||
PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) |
|
||||
PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL));
|
||||
OUT_RING(ring, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |
|
||||
A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
|
||||
A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
|
||||
OUT_RING(ring, 0x0000ffff);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLORCONTROL));
|
||||
OUT_RING(ring, RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
|
||||
RB_COLORCONTROL_BLEND_DISABLE |
|
||||
RB_COLORCONTROL_ROP_CODE(12) |
|
||||
RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
|
||||
RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
|
||||
OUT_RING(ring, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS) |
|
||||
A2XX_RB_COLORCONTROL_BLEND_DISABLE |
|
||||
A2XX_RB_COLORCONTROL_ROP_CODE(12) |
|
||||
A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE) |
|
||||
A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_BLEND_CONTROL));
|
||||
OUT_RING(ring, RB_BLENDCONTROL_COLOR_SRCBLEND(RB_BLEND_ONE) |
|
||||
RB_BLENDCONTROL_COLOR_COMB_FCN(COMB_DST_PLUS_SRC) |
|
||||
RB_BLENDCONTROL_COLOR_DESTBLEND(RB_BLEND_ZERO) |
|
||||
RB_BLENDCONTROL_ALPHA_SRCBLEND(RB_BLEND_ONE) |
|
||||
RB_BLENDCONTROL_ALPHA_COMB_FCN(COMB_DST_PLUS_SRC) |
|
||||
RB_BLENDCONTROL_ALPHA_DESTBLEND(RB_BLEND_ZERO));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
|
||||
OUT_RING(ring, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE) |
|
||||
A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC) |
|
||||
A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO) |
|
||||
A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE) |
|
||||
A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC) |
|
||||
A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
|
||||
OUT_RING(ring, PA_SC_WINDOW_OFFSET_DISABLE |
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
|
||||
OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_DISABLE |
|
||||
xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
|
||||
OUT_RING(ring, xy2d(bin_w, bin_h)); /* PA_SC_WINDOW_SCISSOR_BR */
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_VPORT_XSCALE));
|
||||
OUT_RING(ring, f2d((float)bin_w/2.0)); /* PA_CL_VPORT_XSCALE */
|
||||
OUT_RING(ring, f2d((float)bin_w/2.0)); /* PA_CL_VPORT_XOFFSET */
|
||||
OUT_RING(ring, f2d(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
|
||||
OUT_RING(ring, f2d((float)bin_h/2.0)); /* PA_CL_VPORT_YOFFSET */
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
|
||||
OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XSCALE */
|
||||
OUT_RING(ring, fui((float)bin_w/2.0)); /* PA_CL_VPORT_XOFFSET */
|
||||
OUT_RING(ring, fui(-(float)bin_h/2.0)); /* PA_CL_VPORT_YSCALE */
|
||||
OUT_RING(ring, fui((float)bin_h/2.0)); /* PA_CL_VPORT_YOFFSET */
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL));
|
||||
OUT_RING(ring, PA_CL_VTE_CNTL_VTX_XY_FMT |
|
||||
PA_CL_VTE_CNTL_VTX_Z_FMT | // XXX check this???
|
||||
PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
|
||||
OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT |
|
||||
A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT | // XXX check this???
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
if (ctx->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
|
||||
|
|
@ -395,18 +397,12 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
|
|||
struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
|
||||
struct fd_gmem_stateobj *gmem = &ctx->gmem;
|
||||
struct fd_ringbuffer *ring = ctx->ring;
|
||||
enum rb_colorformatx colorformatx = fd_pipe2color(pfb->cbufs[0]->format);
|
||||
enum a2xx_colorformatx colorformatx = fd_pipe2color(pfb->cbufs[0]->format);
|
||||
uint32_t i, timestamp, yoff = 0;
|
||||
uint32_t base, reg;
|
||||
uint32_t reg;
|
||||
|
||||
calculate_tiles(ctx);
|
||||
|
||||
/* this should be true because bin_w/bin_h should be multiples of 32: */
|
||||
assert(((gmem->bin_w * gmem->bin_h) % 1024) == 0);
|
||||
|
||||
/* depth/stencil starts after color buffer in GMEM: */
|
||||
base = (gmem->bin_w * gmem->bin_h) / 1024;
|
||||
|
||||
DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
|
||||
util_format_name(pfb->cbufs[0]->format),
|
||||
pfb->zsbuf ? util_format_name(pfb->zsbuf->format) : "none");
|
||||
|
|
@ -419,13 +415,13 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
|
|||
* needs to be emitted for each tile:
|
||||
*/
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 4);
|
||||
OUT_RING(ring, CP_REG(REG_RB_SURFACE_INFO));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_SURFACE_INFO));
|
||||
OUT_RING(ring, gmem->bin_w); /* RB_SURFACE_INFO */
|
||||
OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(1) | /* RB_COLOR_INFO */
|
||||
RB_COLOR_INFO_COLOR_FORMAT(colorformatx));
|
||||
reg = RB_DEPTH_INFO_DEPTH_BASE(ALIGN(base, 4));
|
||||
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
|
||||
A2XX_RB_COLOR_INFO_FORMAT(colorformatx));
|
||||
reg = A2XX_RB_DEPTH_INFO_DEPTH_BASE(ALIGN(gmem->bin_w * gmem->bin_h, 4));
|
||||
if (pfb->zsbuf)
|
||||
reg |= RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
|
||||
reg |= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb->zsbuf->format));
|
||||
OUT_RING(ring, reg); /* RB_DEPTH_INFO */
|
||||
|
||||
yoff= gmem->miny;
|
||||
|
|
@ -445,17 +441,9 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
|
|||
DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
|
||||
bh, yoff, bw, xoff);
|
||||
|
||||
if ((i == 0) && (j == 0)) {
|
||||
uint32_t reg;
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
}
|
||||
|
||||
/* setup screen scissor for current tile (same for mem2gmem): */
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_SCREEN_SCISSOR_TL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL));
|
||||
OUT_RING(ring, xy2d(0,0)); /* PA_SC_SCREEN_SCISSOR_TL */
|
||||
OUT_RING(ring, xy2d(bw, bh)); /* PA_SC_SCREEN_SCISSOR_BR */
|
||||
|
||||
|
|
@ -463,23 +451,23 @@ fd_gmem_render_tiles(struct pipe_context *pctx)
|
|||
emit_mem2gmem(ctx, ring, xoff, yoff, bw, bh);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLOR_INFO));
|
||||
OUT_RING(ring, RB_COLOR_INFO_COLOR_SWAP(1) | /* RB_COLOR_INFO */
|
||||
RB_COLOR_INFO_COLOR_FORMAT(colorformatx));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
|
||||
OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
|
||||
A2XX_RB_COLOR_INFO_FORMAT(colorformatx));
|
||||
|
||||
/* setup window scissor and offset for current tile (different
|
||||
* from mem2gmem):
|
||||
*/
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET));
|
||||
OUT_RING(ring, PA_SC_WINDOW_OFFSET_X(-xoff) |
|
||||
PA_SC_WINDOW_OFFSET_Y(-yoff));/* PA_SC_WINDOW_OFFSET */
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
|
||||
OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(-xoff) |
|
||||
A2XX_PA_SC_WINDOW_OFFSET_Y(-yoff));/* PA_SC_WINDOW_OFFSET */
|
||||
|
||||
/* emit IB to drawcmds: */
|
||||
OUT_IB (ring, ctx->draw_start, ctx->draw_end);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
|
||||
OUT_RING(ring, 0x00000000); /* PA_SC_WINDOW_OFFSET */
|
||||
|
||||
/* emit gmem2mem to transfer tile back to system memory: */
|
||||
|
|
|
|||
|
|
@ -1,86 +0,0 @@
|
|||
/* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
|
||||
|
||||
/*
|
||||
* Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Rob Clark <robclark@freedesktop.org>
|
||||
*/
|
||||
|
||||
#ifndef FREEDRENO_PM4_H_
|
||||
#define FREEDRENO_PM4_H_
|
||||
|
||||
#define CP_TYPE0_PKT (0 << 30)
|
||||
#define CP_TYPE1_PKT (1 << 30)
|
||||
#define CP_TYPE2_PKT (2 << 30)
|
||||
#define CP_TYPE3_PKT (3 << 30)
|
||||
|
||||
|
||||
#define CP_ME_INIT 0x48
|
||||
#define CP_NOP 0x10
|
||||
#define CP_INDIRECT_BUFFER 0x3f
|
||||
#define CP_INDIRECT_BUFFER_PFD 0x37
|
||||
#define CP_WAIT_FOR_IDLE 0x26
|
||||
#define CP_WAIT_REG_MEM 0x3c
|
||||
#define CP_WAIT_REG_EQ 0x52
|
||||
#define CP_WAT_REG_GTE 0x53
|
||||
#define CP_WAIT_UNTIL_READ 0x5c
|
||||
#define CP_WAIT_IB_PFD_COMPLETE 0x5d
|
||||
#define CP_REG_RMW 0x21
|
||||
#define CP_REG_TO_MEM 0x3e
|
||||
#define CP_MEM_WRITE 0x3d
|
||||
#define CP_MEM_WRITE_CNTR 0x4f
|
||||
#define CP_COND_EXEC 0x44
|
||||
#define CP_COND_WRITE 0x45
|
||||
#define CP_EVENT_WRITE 0x46
|
||||
#define CP_EVENT_WRITE_SHD 0x58
|
||||
#define CP_EVENT_WRITE_CFL 0x59
|
||||
#define CP_EVENT_WRITE_ZPD 0x5b
|
||||
#define CP_DRAW_INDX 0x22
|
||||
#define CP_DRAW_INDX_2 0x36
|
||||
#define CP_DRAW_INDX_BIN 0x34
|
||||
#define CP_DRAW_INDX_2_BIN 0x35
|
||||
#define CP_VIZ_QUERY 0x23
|
||||
#define CP_SET_STATE 0x25
|
||||
#define CP_SET_CONSTANT 0x2d
|
||||
#define CP_IM_LOAD 0x27
|
||||
#define CP_IM_LOAD_IMMEDIATE 0x2b
|
||||
#define CP_LOAD_CONSTANT_CONTEXT 0x2e
|
||||
#define CP_INVALIDATE_STATE 0x3b
|
||||
#define CP_SET_SHADER_BASES 0x4a
|
||||
#define CP_SET_BIN_MASK 0x50
|
||||
#define CP_SET_BIN_SELECT 0x51
|
||||
#define CP_CONTEXT_UPDATE 0x5e
|
||||
#define CP_INTERRUPT 0x40
|
||||
#define CP_IM_STORE 0x2c
|
||||
#define CP_SET_BIN_BASE_OFFSET 0x4b /* for a20x */
|
||||
#define CP_SET_DRAW_INIT_FLAGS 0x4b /* for a22x */
|
||||
#define CP_SET_PROTECTED_MODE 0x5f
|
||||
#define CP_LOAD_STATE 0x30
|
||||
#define CP_COND_INDIRECT_BUFFER_PFE 0x3a
|
||||
#define CP_COND_INDIRECT_BUFFER_PFD 0x32
|
||||
|
||||
|
||||
#define CP_REG(reg) ((0x4 << 16) | ((reg) - 0x2000))
|
||||
|
||||
|
||||
#endif /* FREEDRENO_PM4_H_ */
|
||||
|
|
@ -301,13 +301,13 @@ fd_program_emit(struct fd_ringbuffer *ring,
|
|||
vs_export = max(1, prog->num_exports) - 1;
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_SQ_PROGRAM_CNTL));
|
||||
OUT_RING(ring, SQ_PROGRAM_CNTL_PS_EXPORT_MODE(POSITION_2_VECTORS_SPRITE) |
|
||||
SQ_PROGRAM_CNTL_VS_RESOURCE |
|
||||
SQ_PROGRAM_CNTL_PS_RESOURCE |
|
||||
SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(vs_export) |
|
||||
SQ_PROGRAM_CNTL_PS_REGS(fs_gprs) |
|
||||
SQ_PROGRAM_CNTL_VS_REGS(vs_gprs));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_SQ_PROGRAM_CNTL));
|
||||
OUT_RING(ring, A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(POSITION_2_VECTORS_SPRITE) |
|
||||
A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE |
|
||||
A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE |
|
||||
A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(vs_export) |
|
||||
A2XX_SQ_PROGRAM_CNTL_PS_REGS(fs_gprs) |
|
||||
A2XX_SQ_PROGRAM_CNTL_VS_REGS(vs_gprs));
|
||||
}
|
||||
|
||||
/* Creates shader:
|
||||
|
|
|
|||
|
|
@ -36,16 +36,16 @@
|
|||
#include "freedreno_util.h"
|
||||
|
||||
|
||||
static enum pa_su_sc_draw
|
||||
static enum adreno_pa_su_sc_draw
|
||||
polygon_mode(unsigned mode)
|
||||
{
|
||||
switch (mode) {
|
||||
case PIPE_POLYGON_MODE_POINT:
|
||||
return DRAW_POINTS;
|
||||
return PC_DRAW_POINTS;
|
||||
case PIPE_POLYGON_MODE_LINE:
|
||||
return DRAW_LINES;
|
||||
return PC_DRAW_LINES;
|
||||
case PIPE_POLYGON_MODE_FILL:
|
||||
return DRAW_TRIANGLES;
|
||||
return PC_DRAW_TRIANGLES;
|
||||
default:
|
||||
DBG("invalid polygon mode: %u", mode);
|
||||
return 0;
|
||||
|
|
@ -75,55 +75,55 @@ fd_rasterizer_state_create(struct pipe_context *pctx,
|
|||
so->base = *cso;
|
||||
|
||||
so->pa_sc_line_stipple = cso->line_stipple_enable ?
|
||||
PA_SC_LINE_STIPPLE_LINE_PATTERN(cso->line_stipple_pattern) |
|
||||
PA_SC_LINE_STIPPLE_REPEAT_COUNT(cso->line_stipple_factor) : 0;
|
||||
A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(cso->line_stipple_pattern) |
|
||||
A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(cso->line_stipple_factor) : 0;
|
||||
|
||||
so->pa_cl_clip_cntl = 0; // TODO
|
||||
|
||||
so->pa_su_vtx_cntl =
|
||||
PA_SU_VTX_CNTL_PIX_CENTER(cso->gl_rasterization_rules ? PIXCENTER_OGL : PIXCENTER_D3D) |
|
||||
PA_SU_VTX_CNTL_QUANT_MODE(ONE_SIXTEENTH);
|
||||
A2XX_PA_SU_VTX_CNTL_PIX_CENTER(cso->gl_rasterization_rules ? PIXCENTER_OGL : PIXCENTER_D3D) |
|
||||
A2XX_PA_SU_VTX_CNTL_QUANT_MODE(ONE_SIXTEENTH);
|
||||
|
||||
so->pa_su_point_size =
|
||||
PA_SU_POINT_SIZE_HEIGHT(cso->point_size/2) |
|
||||
PA_SU_POINT_SIZE_WIDTH(cso->point_size/2);
|
||||
A2XX_PA_SU_POINT_SIZE_HEIGHT(cso->point_size/2) |
|
||||
A2XX_PA_SU_POINT_SIZE_WIDTH(cso->point_size/2);
|
||||
|
||||
so->pa_su_point_minmax =
|
||||
PA_SU_POINT_MINMAX_MIN_SIZE(psize_min/2) |
|
||||
PA_SU_POINT_MINMAX_MAX_SIZE(psize_max/2);
|
||||
A2XX_PA_SU_POINT_MINMAX_MIN(psize_min/2) |
|
||||
A2XX_PA_SU_POINT_MINMAX_MAX(psize_max/2);
|
||||
|
||||
so->pa_su_line_cntl =
|
||||
PA_SU_LINE_CNTL_WIDTH(cso->line_width/2);
|
||||
A2XX_PA_SU_LINE_CNTL_WIDTH(cso->line_width/2);
|
||||
|
||||
so->pa_su_sc_mode_cntl =
|
||||
PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE |
|
||||
PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(polygon_mode(cso->fill_front)) |
|
||||
PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(polygon_mode(cso->fill_back));
|
||||
A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE |
|
||||
A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(polygon_mode(cso->fill_front)) |
|
||||
A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(polygon_mode(cso->fill_back));
|
||||
|
||||
if (cso->cull_face & PIPE_FACE_FRONT)
|
||||
so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_CULL_FRONT;
|
||||
so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT;
|
||||
if (cso->cull_face & PIPE_FACE_BACK)
|
||||
so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_CULL_BACK;
|
||||
so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK;
|
||||
if (!cso->flatshade_first)
|
||||
so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST;
|
||||
so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST;
|
||||
if (!cso->front_ccw)
|
||||
so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_FACE;
|
||||
so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_FACE;
|
||||
if (cso->line_stipple_enable)
|
||||
so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE;
|
||||
so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE;
|
||||
if (cso->multisample)
|
||||
so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_MSAA_ENABLE;
|
||||
so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE;
|
||||
|
||||
if (cso->fill_front != PIPE_POLYGON_MODE_FILL ||
|
||||
cso->fill_back != PIPE_POLYGON_MODE_FILL)
|
||||
so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_POLYMODE(POLY_DUALMODE);
|
||||
so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(POLY_DUALMODE);
|
||||
else
|
||||
so->pa_su_sc_mode_cntl |= PA_SU_SC_MODE_CNTL_POLYMODE(POLY_DISABLED);
|
||||
so->pa_su_sc_mode_cntl |= A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(POLY_DISABLED);
|
||||
|
||||
if (cso->offset_tri)
|
||||
so->pa_su_sc_mode_cntl |=
|
||||
PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE |
|
||||
PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE |
|
||||
PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE;
|
||||
A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE |
|
||||
A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE |
|
||||
A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE;
|
||||
|
||||
return so;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -366,7 +366,7 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty)
|
|||
|
||||
if (dirty & FD_DIRTY_SAMPLE_MASK) {
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_MASK));
|
||||
OUT_RING(ring, ctx->sample_mask);
|
||||
}
|
||||
|
||||
|
|
@ -374,44 +374,44 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty)
|
|||
struct pipe_stencil_ref *sr = &ctx->stencil_ref;
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_DEPTHCONTROL));
|
||||
OUT_RING(ring, ctx->zsa->rb_depthcontrol);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 4);
|
||||
OUT_RING(ring, CP_REG(REG_RB_STENCILREFMASK_BF));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_STENCILREFMASK_BF));
|
||||
OUT_RING(ring, ctx->zsa->rb_stencilrefmask_bf |
|
||||
RB_STENCILREFMASK_STENCILREF(sr->ref_value[1]));
|
||||
A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[1]));
|
||||
OUT_RING(ring, ctx->zsa->rb_stencilrefmask |
|
||||
RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
|
||||
A2XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
|
||||
OUT_RING(ring, ctx->zsa->rb_alpha_ref);
|
||||
}
|
||||
|
||||
if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
|
||||
OUT_RING(ring, ctx->rasterizer->pa_cl_clip_cntl);
|
||||
OUT_RING(ring, ctx->rasterizer->pa_su_sc_mode_cntl |
|
||||
PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE);
|
||||
A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SU_POINT_SIZE));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_POINT_SIZE));
|
||||
OUT_RING(ring, ctx->rasterizer->pa_su_point_size);
|
||||
OUT_RING(ring, ctx->rasterizer->pa_su_point_minmax);
|
||||
OUT_RING(ring, ctx->rasterizer->pa_su_line_cntl);
|
||||
OUT_RING(ring, ctx->rasterizer->pa_sc_line_stipple);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 6);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SU_VTX_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SU_VTX_CNTL));
|
||||
OUT_RING(ring, ctx->rasterizer->pa_su_vtx_cntl);
|
||||
OUT_RING(ring, f2d(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
|
||||
OUT_RING(ring, f2d(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
|
||||
OUT_RING(ring, f2d(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
|
||||
OUT_RING(ring, f2d(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
|
||||
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_CLIP_ADJ */
|
||||
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_VERT_DISC_ADJ */
|
||||
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_CLIP_ADJ */
|
||||
OUT_RING(ring, fui(1.0)); /* PA_CL_GB_HORZ_DISC_ADJ */
|
||||
}
|
||||
|
||||
if (dirty & FD_DIRTY_SCISSOR) {
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL));
|
||||
OUT_RING(ring, xy2d(ctx->scissor.minx, /* PA_SC_WINDOW_SCISSOR_TL */
|
||||
ctx->scissor.miny));
|
||||
OUT_RING(ring, xy2d(ctx->scissor.maxx, /* PA_SC_WINDOW_SCISSOR_BR */
|
||||
|
|
@ -425,23 +425,23 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty)
|
|||
|
||||
if (dirty & FD_DIRTY_VIEWPORT) {
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 7);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_VPORT_XSCALE));
|
||||
OUT_RING(ring, f2d(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */
|
||||
OUT_RING(ring, f2d(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */
|
||||
OUT_RING(ring, f2d(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */
|
||||
OUT_RING(ring, f2d(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */
|
||||
OUT_RING(ring, f2d(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */
|
||||
OUT_RING(ring, f2d(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE));
|
||||
OUT_RING(ring, fui(ctx->viewport.scale[0])); /* PA_CL_VPORT_XSCALE */
|
||||
OUT_RING(ring, fui(ctx->viewport.translate[0])); /* PA_CL_VPORT_XOFFSET */
|
||||
OUT_RING(ring, fui(ctx->viewport.scale[1])); /* PA_CL_VPORT_YSCALE */
|
||||
OUT_RING(ring, fui(ctx->viewport.translate[1])); /* PA_CL_VPORT_YOFFSET */
|
||||
OUT_RING(ring, fui(ctx->viewport.scale[2])); /* PA_CL_VPORT_ZSCALE */
|
||||
OUT_RING(ring, fui(ctx->viewport.translate[2])); /* PA_CL_VPORT_ZOFFSET */
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_CL_VTE_CNTL));
|
||||
OUT_RING(ring, PA_CL_VTE_CNTL_VTX_W0_FMT |
|
||||
PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA |
|
||||
PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA);
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_VTE_CNTL));
|
||||
OUT_RING(ring, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA |
|
||||
A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA);
|
||||
}
|
||||
|
||||
if (dirty & (FD_DIRTY_PROG | FD_DIRTY_VTX | FD_DIRTY_VERTTEX | FD_DIRTY_FRAGTEX)) {
|
||||
|
|
@ -460,17 +460,17 @@ fd_state_emit(struct pipe_context *pctx, uint32_t dirty)
|
|||
|
||||
if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_ZSA)) {
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLORCONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLORCONTROL));
|
||||
OUT_RING(ring, ctx->zsa->rb_colorcontrol | ctx->blend->rb_colorcontrol);
|
||||
}
|
||||
|
||||
if (dirty & FD_DIRTY_BLEND) {
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_BLEND_CONTROL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_CONTROL));
|
||||
OUT_RING(ring, ctx->blend->rb_blendcontrol);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLOR_MASK));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
|
||||
OUT_RING(ring, ctx->blend->rb_colormask);
|
||||
}
|
||||
|
||||
|
|
@ -488,78 +488,78 @@ fd_state_emit_setup(struct pipe_context *pctx)
|
|||
struct fd_context *ctx = fd_context(pctx);
|
||||
struct fd_ringbuffer *ring = ctx->ring;
|
||||
|
||||
OUT_PKT0(ring, REG_TP0_CHICKEN, 1);
|
||||
OUT_PKT0(ring, REG_A2XX_TP0_CHICKEN, 1);
|
||||
OUT_RING(ring, 0x00000002);
|
||||
|
||||
OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
|
||||
OUT_RING(ring, 0x00007fff);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_SQ_VS_CONST));
|
||||
OUT_RING(ring, SQ_VS_CONST_BASE(VS_CONST_BASE) |
|
||||
SQ_VS_CONST_SIZE(0x100));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_SQ_VS_CONST));
|
||||
OUT_RING(ring, A2XX_SQ_VS_CONST_BASE(VS_CONST_BASE) |
|
||||
A2XX_SQ_VS_CONST_SIZE(0x100));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_SQ_PS_CONST));
|
||||
OUT_RING(ring, SQ_PS_CONST_BASE(PS_CONST_BASE) |
|
||||
SQ_PS_CONST_SIZE(0xe0));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_SQ_PS_CONST));
|
||||
OUT_RING(ring, A2XX_SQ_PS_CONST_BASE(PS_CONST_BASE) |
|
||||
A2XX_SQ_PS_CONST_SIZE(0xe0));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_MAX_VTX_INDX));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
|
||||
OUT_RING(ring, 0xffffffff); /* VGT_MAX_VTX_INDX */
|
||||
OUT_RING(ring, 0x00000000); /* VGT_MIN_VTX_INDX */
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, 0x0000003b);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_SQ_CONTEXT_MISC));
|
||||
OUT_RING(ring, SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_SQ_CONTEXT_MISC));
|
||||
OUT_RING(ring, A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(CENTERS_ONLY));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_SQ_INTERPOLATOR_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_SQ_INTERPOLATOR_CNTL));
|
||||
OUT_RING(ring, 0xffffffff);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_AA_CONFIG));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_AA_CONFIG));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_LINE_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_LINE_CNTL));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_OFFSET));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
// XXX we change this dynamically for draw/clear.. vs gmem<->mem..
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_MODECONTROL));
|
||||
OUT_RING(ring, RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_MODECONTROL));
|
||||
OUT_RING(ring, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH));
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_SAMPLE_POS));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_SAMPLE_POS));
|
||||
OUT_RING(ring, 0x88888888);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLOR_DEST_MASK));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_DEST_MASK));
|
||||
OUT_RING(ring, 0xffffffff);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COPY_DEST_INFO));
|
||||
OUT_RING(ring, RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) |
|
||||
RB_COPY_DEST_INFO_WRITE_RED |
|
||||
RB_COPY_DEST_INFO_WRITE_GREEN |
|
||||
RB_COPY_DEST_INFO_WRITE_BLUE |
|
||||
RB_COPY_DEST_INFO_WRITE_ALPHA);
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_DEST_INFO));
|
||||
OUT_RING(ring, A2XX_RB_COPY_DEST_INFO_FORMAT(COLORX_4_4_4_4) |
|
||||
A2XX_RB_COPY_DEST_INFO_WRITE_RED |
|
||||
A2XX_RB_COPY_DEST_INFO_WRITE_GREEN |
|
||||
A2XX_RB_COPY_DEST_INFO_WRITE_BLUE |
|
||||
A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 3);
|
||||
OUT_RING(ring, CP_REG(REG_SQ_WRAPPING_0));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_SQ_WRAPPING_0));
|
||||
OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_0 */
|
||||
OUT_RING(ring, 0x00000000); /* SQ_WRAPPING_1 */
|
||||
|
||||
|
|
@ -572,7 +572,7 @@ fd_state_emit_setup(struct pipe_context *pctx)
|
|||
OUT_RING(ring, 0x5f601000);
|
||||
OUT_RING(ring, 0x00000001);
|
||||
|
||||
OUT_PKT0(ring, REG_SQ_INST_STORE_MANAGMENT, 1);
|
||||
OUT_PKT0(ring, REG_A2XX_SQ_INST_STORE_MANAGMENT, 1);
|
||||
OUT_RING(ring, 0x00000180);
|
||||
|
||||
OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
|
||||
|
|
@ -598,14 +598,14 @@ fd_state_emit_setup(struct pipe_context *pctx)
|
|||
OUT_RING(ring, 0x3e800000);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_RB_COLOR_MASK));
|
||||
OUT_RING(ring, RB_COLOR_MASK_WRITE_RED |
|
||||
RB_COLOR_MASK_WRITE_GREEN |
|
||||
RB_COLOR_MASK_WRITE_BLUE |
|
||||
RB_COLOR_MASK_WRITE_ALPHA);
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_MASK));
|
||||
OUT_RING(ring, A2XX_RB_COLOR_MASK_WRITE_RED |
|
||||
A2XX_RB_COLOR_MASK_WRITE_GREEN |
|
||||
A2XX_RB_COLOR_MASK_WRITE_BLUE |
|
||||
A2XX_RB_COLOR_MASK_WRITE_ALPHA);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 5);
|
||||
OUT_RING(ring, CP_REG(REG_RB_BLEND_RED));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_RB_BLEND_RED));
|
||||
OUT_RING(ring, 0x00000000); /* RB_BLEND_RED */
|
||||
OUT_RING(ring, 0x00000000); /* RB_BLEND_GREEN */
|
||||
OUT_RING(ring, 0x00000000); /* RB_BLEND_BLUE */
|
||||
|
|
|
|||
|
|
@ -87,13 +87,13 @@ fd_sampler_state_create(struct pipe_context *pctx,
|
|||
|
||||
/* SQ_TEX0_PITCH() must be OR'd in later when we know the bound texture: */
|
||||
so->tex0 =
|
||||
SQ_TEX0_CLAMP_X(tex_clamp(cso->wrap_s)) |
|
||||
SQ_TEX0_CLAMP_Y(tex_clamp(cso->wrap_t)) |
|
||||
SQ_TEX0_CLAMP_Z(tex_clamp(cso->wrap_r));
|
||||
A2XX_SQ_TEX_0_CLAMP_X(tex_clamp(cso->wrap_s)) |
|
||||
A2XX_SQ_TEX_0_CLAMP_Y(tex_clamp(cso->wrap_t)) |
|
||||
A2XX_SQ_TEX_0_CLAMP_Z(tex_clamp(cso->wrap_r));
|
||||
|
||||
so->tex3 =
|
||||
SQ_TEX3_XY_MAG_FILTER(tex_filter(cso->mag_img_filter)) |
|
||||
SQ_TEX3_XY_MIN_FILTER(tex_filter(cso->min_img_filter));
|
||||
A2XX_SQ_TEX_3_XY_MAG_FILTER(tex_filter(cso->mag_img_filter)) |
|
||||
A2XX_SQ_TEX_3_XY_MIN_FILTER(tex_filter(cso->min_img_filter));
|
||||
|
||||
so->tex4 = 0x00000000; /* ??? */
|
||||
so->tex5 = 0x00000200; /* ??? */
|
||||
|
|
@ -126,10 +126,10 @@ fd_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
|
|||
so->tex_resource = rsc;
|
||||
so->fmt = fd_pipe2surface(cso->format);
|
||||
|
||||
so->tex0 = SQ_TEX0_PITCH(rsc->pitch);
|
||||
so->tex0 = A2XX_SQ_TEX_0_PITCH(rsc->pitch);
|
||||
so->tex2 =
|
||||
SQ_TEX2_HEIGHT(prsc->height0) |
|
||||
SQ_TEX2_WIDTH(prsc->width0);
|
||||
A2XX_SQ_TEX_2_HEIGHT(prsc->height0 - 1) |
|
||||
A2XX_SQ_TEX_2_WIDTH(prsc->width0 - 1);
|
||||
so->tex3 = fd_tex_swiz(cso->format, cso->swizzle_r, cso->swizzle_g,
|
||||
cso->swizzle_b, cso->swizzle_a);
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ struct fd_sampler_stateobj {
|
|||
struct fd_pipe_sampler_view {
|
||||
struct pipe_sampler_view base;
|
||||
struct fd_resource *tex_resource;
|
||||
enum sq_surfaceformat fmt;
|
||||
enum a2xx_sq_surfaceformat fmt;
|
||||
uint32_t tex0, tex2, tex3;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
|
||||
#include "freedreno_util.h"
|
||||
|
||||
enum sq_surfaceformat
|
||||
enum a2xx_sq_surfaceformat
|
||||
fd_pipe2surface(enum pipe_format format)
|
||||
{
|
||||
switch (format) {
|
||||
|
|
@ -194,7 +194,7 @@ fd_pipe2surface(enum pipe_format format)
|
|||
}
|
||||
}
|
||||
|
||||
enum rb_colorformatx
|
||||
enum a2xx_colorformatx
|
||||
fd_pipe2color(enum pipe_format format)
|
||||
{
|
||||
switch (format) {
|
||||
|
|
@ -289,7 +289,7 @@ fd_pipe2color(enum pipe_format format)
|
|||
}
|
||||
}
|
||||
|
||||
enum rb_depth_format
|
||||
enum a2xx_rb_depth_format
|
||||
fd_pipe2depth(enum pipe_format format)
|
||||
{
|
||||
switch (format) {
|
||||
|
|
@ -344,8 +344,8 @@ fd_tex_swiz(enum pipe_format format, unsigned swizzle_r, unsigned swizzle_g,
|
|||
PIPE_SWIZZLE_ONE, PIPE_SWIZZLE_ONE,
|
||||
};
|
||||
|
||||
return SQ_TEX3_SWIZ_X(tex_swiz(swiz[desc->swizzle[0]])) |
|
||||
SQ_TEX3_SWIZ_Y(tex_swiz(swiz[desc->swizzle[1]])) |
|
||||
SQ_TEX3_SWIZ_Z(tex_swiz(swiz[desc->swizzle[2]])) |
|
||||
SQ_TEX3_SWIZ_W(tex_swiz(swiz[desc->swizzle[3]]));
|
||||
return A2XX_SQ_TEX_3_SWIZ_X(tex_swiz(swiz[desc->swizzle[0]])) |
|
||||
A2XX_SQ_TEX_3_SWIZ_Y(tex_swiz(swiz[desc->swizzle[1]])) |
|
||||
A2XX_SQ_TEX_3_SWIZ_Z(tex_swiz(swiz[desc->swizzle[2]])) |
|
||||
A2XX_SQ_TEX_3_SWIZ_W(tex_swiz(swiz[desc->swizzle[3]]));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -34,13 +34,15 @@
|
|||
|
||||
#include "pipe/p_format.h"
|
||||
#include "util/u_debug.h"
|
||||
#include "util/u_math.h"
|
||||
|
||||
#include "freedreno_pm4.h"
|
||||
#include "freedreno_a2xx_reg.h"
|
||||
#include "adreno_common.xml.h"
|
||||
#include "adreno_pm4.xml.h"
|
||||
#include "a2xx.xml.h"
|
||||
|
||||
enum sq_surfaceformat fd_pipe2surface(enum pipe_format format);
|
||||
enum rb_colorformatx fd_pipe2color(enum pipe_format format);
|
||||
enum rb_depth_format fd_pipe2depth(enum pipe_format format);
|
||||
enum a2xx_sq_surfaceformat fd_pipe2surface(enum pipe_format format);
|
||||
enum a2xx_colorformatx fd_pipe2color(enum pipe_format format);
|
||||
enum a2xx_rb_depth_format fd_pipe2depth(enum pipe_format format);
|
||||
enum pc_di_index_size fd_pipe2index(enum pipe_format format);
|
||||
uint32_t fd_tex_swiz(enum pipe_format format, unsigned swizzle_r,
|
||||
unsigned swizzle_g, unsigned swizzle_b, unsigned swizzle_a);
|
||||
|
|
@ -63,6 +65,26 @@ extern int fd_mesa_debug;
|
|||
#define max(a, b) (((a) > (b)) ? (a) : (b))
|
||||
|
||||
|
||||
#define CP_REG(reg) ((0x4 << 16) | ((unsigned int)((reg) - (0x2000))))
|
||||
|
||||
static inline uint32_t DRAW(enum pc_di_primtype prim_type,
|
||||
enum pc_di_src_sel source_select, enum pc_di_index_size index_size,
|
||||
enum pc_di_vis_cull_mode vis_cull_mode)
|
||||
{
|
||||
return (prim_type << 0) |
|
||||
(source_select << 6) |
|
||||
((index_size & 1) << 11) |
|
||||
((index_size >> 1) << 13) |
|
||||
(vis_cull_mode << 9) |
|
||||
(1 << 14);
|
||||
}
|
||||
|
||||
/* convert x,y to dword */
|
||||
static inline uint32_t xy2d(uint16_t x, uint16_t y)
|
||||
{
|
||||
return ((y & 0x3fff) << 16) | (x & 0x3fff);
|
||||
}
|
||||
|
||||
#define LOG_DWORDS 0
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -198,15 +198,15 @@ fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
|
|||
emit_vertexbufs(ctx, info->count);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
|
||||
OUT_RING(ring, info->start);
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
|
||||
OUT_RING(ring, 0x0000003b);
|
||||
|
||||
OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1);
|
||||
OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE);
|
||||
OUT_PKT0(ring, REG_A2XX_TC_CNTL_STATUS, 1);
|
||||
OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
|
||||
|
||||
OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
|
||||
OUT_RING(ring, 0x0000000);
|
||||
|
|
@ -222,7 +222,7 @@ fd_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
|
|||
}
|
||||
|
||||
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
|
||||
OUT_RING(ring, CP_REG(REG_2010));
|
||||
OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010));
|
||||
OUT_RING(ring, 0x00000000);
|
||||
|
||||
emit_cacheflush(ring);
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
#include "freedreno_context.h"
|
||||
#include "freedreno_util.h"
|
||||
|
||||
static enum rb_stencil_op
|
||||
static enum adreno_stencil_op
|
||||
stencil_op(unsigned op)
|
||||
{
|
||||
switch (op) {
|
||||
|
|
@ -74,48 +74,48 @@ fd_zsa_state_create(struct pipe_context *pctx,
|
|||
so->base = *cso;
|
||||
|
||||
so->rb_depthcontrol |=
|
||||
RB_DEPTHCONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
|
||||
A2XX_RB_DEPTHCONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
|
||||
|
||||
if (cso->depth.enabled)
|
||||
so->rb_depthcontrol |= RB_DEPTHCONTROL_Z_ENABLE;
|
||||
so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_ENABLE;
|
||||
if (cso->depth.writemask)
|
||||
so->rb_depthcontrol |= RB_DEPTHCONTROL_Z_WRITE_ENABLE;
|
||||
so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE;
|
||||
|
||||
if (cso->stencil[0].enabled) {
|
||||
const struct pipe_stencil_state *s = &cso->stencil[0];
|
||||
|
||||
so->rb_depthcontrol |=
|
||||
RB_DEPTHCONTROL_STENCIL_ENABLE |
|
||||
RB_DEPTHCONTROL_STENCILFUNC(s->func) | /* maps 1:1 */
|
||||
RB_DEPTHCONTROL_STENCILFAIL(stencil_op(s->fail_op)) |
|
||||
RB_DEPTHCONTROL_STENCILZPASS(stencil_op(s->zpass_op)) |
|
||||
RB_DEPTHCONTROL_STENCILZFAIL(stencil_op(s->zfail_op));
|
||||
A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE |
|
||||
A2XX_RB_DEPTHCONTROL_STENCILFUNC(s->func) | /* maps 1:1 */
|
||||
A2XX_RB_DEPTHCONTROL_STENCILFAIL(stencil_op(s->fail_op)) |
|
||||
A2XX_RB_DEPTHCONTROL_STENCILZPASS(stencil_op(s->zpass_op)) |
|
||||
A2XX_RB_DEPTHCONTROL_STENCILZFAIL(stencil_op(s->zfail_op));
|
||||
so->rb_stencilrefmask |=
|
||||
0xff000000 | /* ??? */
|
||||
RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
|
||||
RB_STENCILREFMASK_STENCILMASK(s->valuemask);
|
||||
A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
|
||||
A2XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);
|
||||
|
||||
if (cso->stencil[1].enabled) {
|
||||
const struct pipe_stencil_state *bs = &cso->stencil[1];
|
||||
|
||||
so->rb_depthcontrol |=
|
||||
RB_DEPTHCONTROL_BACKFACE_ENABLE |
|
||||
RB_DEPTHCONTROL_STENCILFUNC_BF(bs->func) | /* maps 1:1 */
|
||||
RB_DEPTHCONTROL_STENCILFAIL_BF(stencil_op(bs->fail_op)) |
|
||||
RB_DEPTHCONTROL_STENCILZPASS_BF(stencil_op(bs->zpass_op)) |
|
||||
RB_DEPTHCONTROL_STENCILZFAIL_BF(stencil_op(bs->zfail_op));
|
||||
A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE |
|
||||
A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(bs->func) | /* maps 1:1 */
|
||||
A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(stencil_op(bs->fail_op)) |
|
||||
A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(stencil_op(bs->zpass_op)) |
|
||||
A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(stencil_op(bs->zfail_op));
|
||||
so->rb_stencilrefmask_bf |=
|
||||
0xff000000 | /* ??? */
|
||||
RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |
|
||||
RB_STENCILREFMASK_STENCILMASK(bs->valuemask);
|
||||
A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(bs->writemask) |
|
||||
A2XX_RB_STENCILREFMASK_STENCILMASK(bs->valuemask);
|
||||
}
|
||||
}
|
||||
|
||||
if (cso->alpha.enabled) {
|
||||
so->rb_colorcontrol =
|
||||
RB_COLORCONTROL_ALPHA_FUNC(cso->alpha.func) |
|
||||
RB_COLORCONTROL_ALPHA_TEST_ENABLE;
|
||||
so->rb_alpha_ref = f2d(cso->alpha.ref_value);
|
||||
A2XX_RB_COLORCONTROL_ALPHA_FUNC(cso->alpha.func) |
|
||||
A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE;
|
||||
so->rb_alpha_ref = fui(cso->alpha.ref_value);
|
||||
}
|
||||
|
||||
return so;
|
||||
|
|
|
|||
|
|
@ -48,13 +48,12 @@ void fd_zsa_init(struct pipe_context *pctx);
|
|||
|
||||
static inline bool fd_depth_enabled(struct fd_zsa_stateobj *zsa)
|
||||
{
|
||||
return !!(zsa->rb_depthcontrol & RB_DEPTHCONTROL_Z_ENABLE);
|
||||
return zsa->base.depth.enabled;
|
||||
}
|
||||
|
||||
static inline bool fd_stencil_enabled(struct fd_zsa_stateobj *zsa)
|
||||
{
|
||||
//RB_DEPTHCONTROL_STENCIL_ENABLE
|
||||
return !!(zsa->rb_depthcontrol & RB_DEPTHCONTROL_STENCIL_ENABLE);
|
||||
return zsa->base.stencil[0].enabled;
|
||||
}
|
||||
|
||||
#endif /* FREEDRENO_ZSA_H_ */
|
||||
|
|
|
|||
|
|
@ -21,13 +21,16 @@
|
|||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef INSTR_H_
|
||||
#define INSTR_H_
|
||||
|
||||
#include "freedreno_a2xx_reg.h"
|
||||
#ifndef INSTR_A2XX_H_
|
||||
#define INSTR_A2XX_H_
|
||||
|
||||
#define PACKED __attribute__((__packed__))
|
||||
|
||||
#include "util/u_math.h"
|
||||
#include "adreno_common.xml.h"
|
||||
#include "a2xx.xml.h"
|
||||
|
||||
|
||||
/*
|
||||
* ALU instructions:
|
||||
*/
|
||||
|
|
@ -301,7 +304,7 @@ typedef enum {
|
|||
SAMPLE_CENTER = 1,
|
||||
} instr_sample_loc_t;
|
||||
|
||||
typedef enum sq_surfaceformat instr_surf_fmt_t;
|
||||
typedef enum a2xx_sq_surfaceformat instr_surf_fmt_t;
|
||||
|
||||
typedef struct PACKED {
|
||||
/* dword0: */
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
#include <assert.h>
|
||||
|
||||
#include "freedreno_util.h"
|
||||
#include "instr.h"
|
||||
#include "instr-a2xx.h"
|
||||
|
||||
#define DEBUG_MSG(f, ...) do { if (0) DBG(f, ##__VA_ARGS__); } while (0)
|
||||
#define WARN_MSG(f, ...) DBG("WARN: "f, ##__VA_ARGS__)
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "instr.h"
|
||||
#include "instr-a2xx.h"
|
||||
|
||||
/* low level intermediate representation of an adreno shader program */
|
||||
|
||||
|
|
@ -76,7 +76,7 @@ struct ir_instruction {
|
|||
unsigned const_idx;
|
||||
/* maybe vertex fetch specific: */
|
||||
unsigned const_idx_sel;
|
||||
enum sq_surfaceformat fmt;
|
||||
enum a2xx_sq_surfaceformat fmt;
|
||||
bool is_signed : 1;
|
||||
bool is_normalized : 1;
|
||||
uint32_t stride;
|
||||
|
|
@ -219,7 +219,7 @@ ir_instr_create_alu(struct ir_cf *cf, instr_vector_opc_t vop, instr_scalar_opc_t
|
|||
}
|
||||
static inline struct ir_instruction *
|
||||
ir_instr_create_vtx_fetch(struct ir_cf *cf, int ci, int cis,
|
||||
enum sq_surfaceformat fmt, bool is_signed, int stride)
|
||||
enum a2xx_sq_surfaceformat fmt, bool is_signed, int stride)
|
||||
{
|
||||
struct ir_instruction *instr = instr = ir_instr_create(cf, IR_FETCH);
|
||||
instr->fetch.opc = VTX_FETCH;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue